A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

A semiconductor device includes: a wiring board including first to third bonding pads; a chip stack including semiconductor chips, each chip having first to third connection pads, the first connection pads being connected in series to each other and to the first bonding pad through first bonding wires to form a first transmission channel, the second connection pads being connected in series to each other and to the second bonding pad through second bonding wires to form a second transmission channel, and the third connection pads being connected in series to each other and to the third bonding pad through third bonding wires to form a third transmission channel; and at least one of a first and a second terminating resistor being provided above the chip stack, the first resistor being connected to the first and second channels, the second resistor being connected to the first and third channels.

A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties.

An electronic component mounting package includes a semiconductor element which is disposed such that an active surface faces a main surface of a wiring portion, and which is electrically connected to the wiring portion via a first terminal; and a thin film passive element which is disposed between the active surface of the semiconductor element and the main surface of the wiring portion when seen in a lamination direction, and which is electrically connected to the semiconductor element. A part of the first terminal is disposed on an outer side with respect to the thin film passive element in a plan view. A length of the first terminal in the lamination direction disposed on the outer side with respect to the thin film passive element is larger than a thickness of the thin film passive element in the lamination direction.

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.

This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.