A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.

A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

The present invention provides a thin film capacitor including a first electrode layer, a second electrode layer, and a dielectric layer provided between the first electrode layer and the second electrode layer, wherein a ratio (S/S.sub.0) of a surface area S of a surface of the first electrode layer on an opposite side to the dielectric layer to a projected area S.sub.0 in a thickness direction of the first electrode layer is 1.01 to 5.00.

A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.

A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

A thin film LC component includes a substrate that has a first surface and a second surface opposing to each other, a thin film capacitor that is formed on the first surface by a thin film process, a thin film inductor that is formed in a region of the second surface by a thin film process, the region at least partially overlapping the thin film capacitor when viewed in plan, interlayer connection conductors that are formed in the substrate and connect the thin film capacitor and the thin film inductor to each other, an insulating layer that is formed over the first surface and covers the thin film capacitor, and a plurality of terminal electrodes that are formed on a surface of the insulating layer and are connected to the thin film capacitor and the thin film inductor.

To provide a thin film capacitor having high adhesion performance with respect to a multilayer substrate. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. A height of the first electrode layer is lower than a height of the second electrode layer. This enhances adhesion performance when the thin film capacitor is embedded in a multilayer substrate and improves ESR characteristics.