H01L2924/1902

Common-mode choke for paralleled power semiconductor

A power module includes a plurality of switching devices. The switching devices are electrically coupled in parallel and triggered by a common gate signal. The switching devices are further attached to a substrate that includes a first coil and a second coil formed around a common axis to define a common mode choke in a gate path and a Kelvin source/emitter path of each of the switching devices.

ELECTRONIC PACKAGE AND ELECTRONIC DEVICE HAVING THE ELECTRONIC PACKAGE
20190319347 · 2019-10-17 ·

An electronic package includes: a carrier structure; a first electronic component disposed on the carrier structure; a first insulating layer formed on the carrier structure; a first antenna structure coupled to the first insulating layer and electrically connected to the first electronic component; and a second antenna structure embedded in the carrier structure. As such, the electronic package provides more antenna functions within a limited space so as to improve the signal quality and transmission rate of electronic products. An electronic device having the electronic package is also provided. The electronic device is applicable to an electronic product having an antenna function.

COMMON-MODE CHOKE FOR PARALLELED POWER SEMICONDUCTOR
20190222118 · 2019-07-18 ·

A power module includes a plurality of switching devices. The switching devices are electrically coupled in parallel and triggered by a common gate signal. The switching devices are further attached to a substrate that includes a first coil and a second coil formed around a common axis to define a common mode choke in a gate path and a Kelvin source/emitter path of each of the switching devices.

HIGH-POWER AMPLIFIER PACKAGE

Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may have cut-outs that allow high-power components to be mounted directly on a heat slug below the laminate. Electrical connections to circuitry on the laminate may be made with wire bonds. The packaging allows more flexible design and tuning of packaged microwave circuitry.

High-power amplifier package

Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may have cut-outs that allow high-power components to be mounted directly on a heat slug below the laminate. Electrical connections to circuitry on the laminate may be made with wire bonds. The packaging allows more flexible design and tuning of packaged microwave circuitry.

Passive within via

A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core

A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

METHODS OF FORMING AN INDUCTOR RF ISOLATION STRUCTURE IN AN INTERPOSER
20250357304 · 2025-11-20 ·

A semiconductor structure includes an interposer including redistribution wiring interconnects and redistribution insulating layers; a first semiconductor die attached to the interposer through a first array of solder material portions; and a second semiconductor die attached to the interposer through a second array of solder material portions. The interposer includes at least one inductor structure located between an area of the first array of solder material portions and an area of the second array of solder material portions in a plan view and laterally encloses a respective area in the plan view.