A semiconductor package (1, 1, 1), the package (1, 1, 1) comprising a first substrate (2) comprising at a front cavity side (5) a plurality of cavities (6, 6), each of the cavities (6, 6) having a bottom wall (7) and side walls (8), and having a conductive path (10) forming an electric contact surface (9) located at the inner side of the bottom wall (7) of the cavity (6, 6), a plurality of semiconductor elements (16, 7), each of the semiconductor elements (16, 17) comprising a first electric contact surface (9) on a first side (26) and a second electric contact surface (9) on a second side (28) opposite to the first side (26), wherein at least one of the semiconductor elements (16, 17) is placed within a corresponding cavity (6, 6) at the front cavity side (5) of the first substrate (2), wherein the first electric contact (27) of the semiconductor element (16, 17) and the electric contact surface (9) at the inner side of the bottom wall (7) of the corresponding cavity (6, 6) are electrically conductive bonded in a material-locking manner, and a second substrate (3), the second substrate (3) being attached with a connection side (12, 13) to the front cavity side (5) of the first substrate (2) thereby encapsulating the semiconductor elements (16, 17) located within the corresponding cavities (6, 6) at the front cavity side (5) of the first substrate (2).

A power amplifier device for a magnetic resonance device includes a circuit board with at least one power amplifier module, and at least one electronics structure including coupled conductor paths arranged on opposing sides of the circuit board. The power amplifier device also includes a cooling plate operable for cooling components on the circuit board that heat up during operation and abutting the circuit board on one side. The cooling plate has a depression that follows the course of the conductor path and faces the conductor path in the region of the conductor path of the electronics structure that is arranged on the side of the circuit board facing the cooling plate.

A switch includes an input contact and an output contact to a conducting channel. At least one of the input and output contacts is capacitively coupled to the conducting channel. A control contact is located outside of a region between the input and output contacts, and can be used to adjust the switch between on and off operating states. The switch can be implemented as a radio frequency switch in a circuit.

The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.

An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required.

The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.

An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required.