Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.

The present disclosure relates to a package structure and a method for forming the same. The package structure includes: a first surface and a second surface that are opposite, passive devices mounted on the first surface of the substrate; a first molding layer encapsulating the passive devices and covering the first surface of the substrate; a first chip comprising a back face and a functional face that are opposite; metal connection structures each comprising a horizontal metal strip and a vertical metal pin electrically connected to the horizontal metal strip; a second molding layer encapsulating the metal connection structures and the first chip and covering the second surface of the substrate; and first solder bumps on the exposed top surfaces of the external terminals.

The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased.

A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.

A package structure and a formation method are provided. The method includes disposing a chip-containing structure over a substrate. The method also includes attaching a heat dissipation structure to the substrate through an adhesive structure. The heat dissipation structure, the substrate, and the adhesive structure together surround a first space containing the chip-containing structure. The adhesive structure has a through-hole connecting the first space to a second space outside of the first space.

Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer/deserializer blocks, using the TVs.

A package comprising a substrate comprising a first surface and a second surface, wherein the substrate comprises a plurality of interconnects; a first antenna device coupled to the first surface of the substrate, through a first plurality of solder interconnects, wherein a portion of the first antenna device overhangs over the substrate such that a portion of the first antenna device does not vertically overlap with any portion of the substrate; a second antenna device coupled to the first surface of the substrate, through a second plurality of solder interconnects; an integrated device coupled to the second surface of the substrate; an encapsulation layer coupled to the second surface of the substrate, wherein a vertical surface of the encapsulation layer is coplanar with a vertical surface of the substrate, and wherein the encapsulation layer at least partially encapsulates the integrated device; and a shield coupled to a surface of the encapsulation layer.

A semiconductor package includes a package substrate including a base substrate including a redistribution layer, pads disposed on first and second surfaces of the base substrate and connected to the redistribution layer, and a protective layer having a mounting region in which first openings respectively exposing first pads among the pads and a second opening exposing second pads among the pads and a portion of the second surface are disposed on the second surface; a semiconductor chip disposed on the mounting region and connected to the pads through the first openings and the second opening; and a sealing material covering a portion of the semiconductor chip and extending into the second opening. Four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region. The second opening is disposed to divide the four first openings into at least two groups.

In some aspects, an integrated circuit (IC) includes a substrate, a plurality of pads including at least two deep trench capacitor (DTC) pads disposed on the substrate, a plurality of first metal layer contacts disposed on the DTC pads, a first solder resist (SR) layer disposed on the substrate, the pads and the first metal layer contacts, a plurality of second metal layer contacts disposed on the first metal layer contacts, a second SR layer disposed on the first SR layer and the second metal layer contacts, and a DTC coupled to the second metal layer contacts.