H01L2924/20104

COVER FILM AND APPLICATION THEREOF
20190244927 · 2019-08-08 ·

A cover film includes a release layer and a polyimide layer disposed on the release layer. The polyimide layer includes an inner surface and an outer surface opposite to the inner surface. The outer surface is exposed to the atmosphere, and the polyimide layer is formed from a reaction of a polyimide composition made of diamine monomer and tetracarboxylic dianhydride monomer. The polyimide layer further includes a cross-linker and an initiator. The diamine monomer is an aliphatic diamine monomer with a number of carbon greater than or equal to 36. A lowest viscosity of the polyimide layer is less than 20000 Pa.Math.s when polyimide layer is under a temperature in a range of 60 C. to 160 C.

SOLID-STATE STORAGE DEVICE
20190229036 · 2019-07-25 ·

A solid-state storage device includes a housing, a wiring board and a semiconductor package unit. The housing is formed with a heat-dissipating recess thereon. The wiring board is fixed in the housing. One side of the semiconductor package unit is mounted on the wiring board, and the other side of the semiconductor package unit is embedded in the heat-dissipating recess. A top surface and lateral surfaces surrounding the top surface of the semiconductor package unit are all thermally connected to the housing in the heat-dissipating recess.

No clean flux composition and methods for use thereof

A flux formulation includes an activator and a protic solvent. The activator may be glutaric acid, levulinic acid, 2-ketobutyric acid, 2-oxovaleric acid, or mixtures thereof. Suitable protic solvents include alkanediol, alkoxy propanol and alkoxy ethanol. The flux formulation may be a no-clean flux formulation that may be used in the soldering of electronic circuit board assemblies, for example, in conjunction with a support fixture having a planar back surface that minimizes vibrations during processing that might otherwise cause misalignment between a chip and a substrate prior to solder reflow.

Systems and methods for bonding semiconductor elements

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.

Method for fabricating hybrid bonded structure

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

Redistribution layer and integrated circuit including redistribution layer

A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

DYE AND PRY PROCESS FOR REMOVING QUAD FLAT NO-LEAD PACKAGES AND BOTTOM TERMINATION COMPONENTS

Embodiments of the invention include a dye and pry process for removing quad flat no-lead (QFN) packages and bottom termination components (BTC) from card assemblies. Aspects of the invention include immersing a semiconductor package assembly in a solution comprising dye and placing the immersed semiconductor package assembly under vacuum pressure. Vacuum conditions ensure that the dye solution is pulled into any cracks in the solder formed between the semiconductor package assembly and the QFN package or BTC. The package assembly is dried and a hole is drilled to expose a bottom surface of the QFN package or BTC. The QFN package or BTC is then removed by applying a force to the exposed bottom surface. The semiconductor package assembly can then be inspected for the dye to locate cracks.

HYBRID BONDED STRUCTURE

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

Systems and methods for bonding semiconductor elements

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures.

Method of manufacturing bonded body

A method of manufacturing a bonded body in which a first body and a second body are bonded using a glass paste. The glass paste includes a crystallized glass frit (A) and a solvent (B). A remelting temperature of the crystallized glass frit (A) is higher than a crystallization temperature thereof which is higher than a glass transition temperature thereof. The method includes: applying the glass paste on at least one of the first and second bodies, bonding the first and second bodies by interposing the glass paste therebetween, heating the bonded first and second bodies to a temperature that is not lower than the crystallization temperature and lower than the remelting temperature of the crystallized glass frit (A), and obtaining the bonded body by cooling the bonded first and second bodies to a temperature that is not higher than the glass transition temperature of the crystallized glass frit.