A semiconductor device production method includes forming a first recess portion in a first insulating film formed on a first substrate and a first conductive layer on the front surface of the first insulating film located inside and outside the first recess portion. In the first recess portion, a first pad is formed having a width of 3 μm or less and including the first conductive layer by performing a first polishing the first conductive layer at a first polishing rate and, after the first polishing, a second polishing the first conductive layer at a second polishing rate lower than the first polishing rate. The first pad of the first substrate and a second pad of a second substrate are joined together by annealing the first substrate and the second substrate. The selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4.

There is provided a bonding wire that improves bonding reliability of a ball bonded part and ball formability and is suitable for on-vehicle devices. The bonding wire for a semiconductor includes a Cu alloy core material, and a Pd coating layer formed on a surface of the Cu alloy core material, and is characterized in that the Cu alloy core material contains Ni, a concentration of Ni is 0.1 to 1.2 wt. % relative to the entire wire, and a thickness of the Pd coating layer is 0.015 to 0.150 m.

There is provided a bonding wire that improves bonding reliability of a ball bonded part and ball formability and is suitable for on-vehicle devices. The bonding wire for a semiconductor includes a Cu alloy core material, and a Pd coating layer formed on a surface of the Cu alloy core material, and is characterized in that the Cu alloy core material contains Ni, a concentration of Ni is 0.1 to 1.2 wt. % relative to the entire wire, and a thickness of the Pd coating layer is 0.015 to 0.150 m.

Provided are a device packing facility and method using DEHT and a device processing apparatus utilizing the DEHT. The device packaging facility includes a mounting unit providing bis(2-ethylhexyl) terephthalate (DEHT) between first and second devices to attach the first and second devices to each other, a processing unit thermally processing the first and second devices that are attached to each other to remove the DEHT and fix the first and second devices to each other, and a transfer unit transferring the first and second devices that are attached to each other from the mounting unit to the processing unit.

A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a second bonding structure. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. The first dielectric layer is hybrid bonded to the second dielectric layer. The first connectors are hybrid bonded to the second connectors. The encapsulant laterally encapsulates the second die. The TIVs penetrate through the encapsulant and are connected to the first bonding structure.

A flip chip bonding method includes obtaining a die including a first substrate and an adhesive layer on the first substrate; bonding the die to a second substrate different from the first substrate; and curing the adhesive layer. The curing the adhesive layer includes heating the second substrate to melt the adhesive layer, and providing the adhesive layer and the second substrate with air having pressure greater than atmospheric pressure.

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient. The method additionally includes bonding the first and the second substrates by contacting the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate to form a substrate assembly. The method further includes post-bond annealing the assembly.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 m in thickness.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 m in thickness.