A solder reflow apparatus includes a vapor generating chamber configured to accommodate a heat transfer fluid and to accommodate saturated vapor generated by heating the heat transfer fluid; a heater configured to heat the heat transfer fluid accommodated in the vapor generating chamber; a substrate stage configured to be movable upward and downward within the vapor generating chamber, the substrate stage including a seating surface; vapor passages penetrating the substrate stage and configured to allow the vapor to move therethrough; and suction passages penetrating the substrate stage to be open to the seating surface and in which at least a partial vacuum is generated.

A semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. The conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85?, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.

A SiP-type electronic device, including an electronic chip provided with an electrical interconnection face; a redistribution layer electrically coupled to the electrical interconnection face of the chip; electrical connection elements electrically coupled to the chip by the redistribution layer which is arranged between the chip and the connection elements; a first metal layer arranged on the side of a second face of the chip and secured to this second face; an encapsulation material arranged around the chip, between the redistribution layer and the first metal layer; a second metal layer including a first face secured by direct bonding to the first metal layer; a substrate arranged against a second face of the second metal layer.

There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

A solder paste that contains or consists of (i) 10-30% by weight of at least one type of particles that each contain a phosphorus fraction of >0 to 500 wt-ppm and are selected from copper particles, copper-rich copper/zinc alloy particles, and copper-rich copper/tin alloy particles, (ii) 60-80% by weight of at least one type of particles selected from tin particles, tin-rich tin/copper alloy particles, tin-rich tin/silver alloy particles, and tin-rich tin/copper/silver alloy particles, and (iii) 3-30% by weight solder flux, in which the mean particle diameter of metallic particles (i) and (ii) is 15 m.

A wafer bonding method includes providing a first wafer including a first wafer surface, forming a first metal layer on the first wafer surface, and forming a first annular retaining wall structure including a first annular retaining wall and a second annular retaining wall surrounded by the first annular retaining wall. The first metal layer is formed between the first annular retaining wall and the second annular retaining wall. The method includes providing a second wafer including a second wafer surface, forming a second metal layer on the second wafer surface, and forming a second annular retaining wall structure including a third annular retaining wall and a fourth annular retaining wall surrounded by the third annular retaining wall. The second metal layer is formed between the third annular retaining wall and the fourth annular retaining wall. The method further includes bonding the first metal layer to the second metal layer.

A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and an electronic component. A curing degree curve is created. The curing degree curve indicates, with respect to each of heating temperatures, relationship between heating time and curing degree of the thermosetting resin. On the basis of the created curing degree curve, a void removal time of a void naturally moving upward in the thermosetting resin, at a first heating temperature, is calculated. The first heating temperature is one of the heating temperatures.

A semiconductor device includes: a base material having a first terminal; a semiconductor chip having a first electrode pad electrically connected with the first terminal, a second electrode pad to which a power supply potential is to be supplied, and a third electrode pad to which a reference potential is to be supplied, and mounted on the base material via a first member; a chip capacitor having a first electrode and a second electrode, and mounted on the semiconductor chip via a second member; a first wire electrically connecting the first electrode pad with the first terminal; a second wire electrically connecting the second electrode pad with the first electrode without going through the base material; and a third wire electrically connecting the third electrode pad with the second electrode without going through the base material.

A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.