A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a second bonding structure. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. The first dielectric layer is hybrid bonded to the second dielectric layer. The first connectors are hybrid bonded to the second connectors. The encapsulant laterally encapsulates the second die. The TIVs penetrate through the encapsulant and are connected to the first bonding structure.

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 m in thickness.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 m in thickness.

An assembly that includes a first substrate, a second substrate, and a stress mitigation layer disposed between the first and the second substrates. The stress mitigation layer is directly bonded onto the second substrate, and the second substrate is separated from the intermetallic compound layer by the stress mitigation layer. The stress mitigation layer has a high purity of at least 99% aluminum such that the stress mitigation layer reduces thermomechanical stresses on the first and second substrates. The assembly further includes an intermetallic compound layer disposed between the first substrate and the stress mitigation layer such that the stress mitigation layer is separated from the first substrate by the intermetallic compound layer.

A method of designing a layout includes determining a first layout pattern, wherein the first layout pattern corresponds to a plurality of contact pads. The method further includes generating a second layout pattern. The method further includes checking whether an edge of the second layout pattern overlaps the first layout pattern. The method further includes adjusting the second layout pattern so that the edge of the second layout pattern overlaps the first layout pattern in response to a determination that the edge of the second layout pattern is separated from the first layout pattern.

The present invention provides a Cu alloy bonding wire for a semiconductor device, where the bonding wire can satisfy requirements of high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device, the abundance ratio of a crystal orientation <110> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis to crystal orientations on a wire surface is 25% or more and 70% or less in average area percentage.

The present invention provides a Cu alloy bonding wire for a semiconductor device, where the bonding wire can satisfy requirements of high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device, the abundance ratio of a crystal orientation <110> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis to crystal orientations on a wire surface is 25% or more and 70% or less in average area percentage.

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

A bonding wire for a semiconductor device, characterized in that the bonding wire includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, the bonding wire contains an element that provides bonding reliability in a high-temperature environment, and a strength ratio defined by the following Equation (1) is 1.1 to 1.6:
Strength ratio=ultimate strength/0.2% offset yield strength.(1)