H01L2924/20108

HYBRID BONDED STRUCTURE

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

SEMICONDUCTOR DEVICE WITH POST PASSIVATION STRUCTURE

A semiconductor structure includes a first contact pad over a passivation layer, wherein the first contact pad is in a circuit region. The semiconductor structure further includes a plurality of second contact pads over the passivation layer, wherein each second contact pad of the plurality of second contact pads is in a non-circuit region. The semiconductor structure further includes a first buffer layer over the first contact pad and over a first second contact pad of the plurality of second contact pads. The semiconductor structure further includes a second buffer layer over the first buffer layer, the first contact pad, the first second contact pad and a portion of a second second contact pad of the plurality of second contact pads, wherein the second buffer layer exposes a portion of the second second contact pad of the plurality of second contact pads.

CONDUCTIVE PASTE AND DIE BONDING METHOD
20190139930 · 2019-05-09 ·

Provided are: a conductive paste in which sinterability of silver particles the conductive paste can be easily controlled by using silver particles having predetermined crystal transformation characteristics defined by an XRD analysis, and after a sintering treatment, excellent electrical conductivity and thermal conductivity can be stably obtained; and a die bonding method using the conductive paste.

Disclosed is a conductive paste which includes silver particles having a volume average particle size of 0.1 to 30 m as a sinterable conductive material, and a dispersing medium for making a paste-like form, and in which when the integrated intensity of the peak at 2=380.2 in the X-ray diffraction chart obtainable by an XRD analysis before a sintering treatment of the silver particles is designated as S1, and the integrated intensity of the peak at 2=380.2 in the X-ray diffraction chart obtainable by an XRD analysis after a sintering treatment (250 C., 60 minutes) of the silver particles is designated as S2, the value of S2/S1 is adjusted to a value within the range of 0.2 to 0.8.

Nickel particle composition, bonding material, and bonding method in which said material is used

A nickel particle composition is shown, including: A) a nickel particle having an average particle size in the range of 0.5 m to 20 m obtained via a laser diffraction/scattering method and containing 50 wt % or more of a nickel element; B) a nickel fine particle having an average primary particle size in the range of 30 nm to 200 nm observed via a scanning electron microscope and containing 50 wt % or more of a nickel element; and C) an organic binder in the range of 0.1 wt % to 2.5 wt % relative to the total metal content; and the weight ratio of a component A to a component B (component A:component B) is in the range of 30:70 to 70:30.

Vertical nanoribbon array (VERNA) thermal interface materials with enhanced thermal transport properties

A thermal interface material (TIM) and method for manufacture is disclosed. A vertically aligned carbon nanotube (VACNT) array is formed on a substrate, then individual CNTs are cleaved to form a vertical nanoribbon array (VERNA). An array of aligned, upright, flat, highly-compliant ribbon elements permit a higher packing density, better ribbon-to-ribbon engagement factor, better contact with adjoining surfaces and potentially achievement of theoretical thermal conductance limit (1 GW/m2K) for such nanostructured polycyclic carbon materials. Methods for forming the VERNA include either or both of electrochemical and gas phase processing steps.

Semiconductor device with post passivation structure and fabrication method therefor

A method of fabricating a semiconductor device includes forming a first contact pad and a second contact pad over a first passivation layer, depositing a first buffer layer over the first contact pad and the second contact pad, and depositing a second buffer layer over the first buffer layer and the second contact pad. The first contact pad is in a circuit region and the second contact pad is in a non-circuit region. An edge of the second contact pad is exposed and a periphery of the first contact pad and an edge of the second contact pad are covered by the first buffer layer.

SOLDER STRUCTURE WITH DISRUPTABLE COATING AS SOLDER SPREADING PROTECTION

A solder structure and method is disclosed. In one example, the solder structure includes a solder material, and a coating which at least partially coats the solder material and is configured for protecting the solder material against solder spreading. The coating is at least partially disrupted when establishing a solder connection between the solder material and a solderable structure.

Electronic device interconnections for high temperature operability

Systems and methods are disclosed for providing an interconnection for extending high-temperature use in sensors and other electronic devices. The interconnection includes a semiconductor layer; an ohmic contact layer disposed on a first region of the semiconductor layer; an insulating layer disposed on a second region of the semiconductor layer, where the second region differs from the first region; a metal layer disposed above at least the insulating layer and the ohmic contact layer; and a connecting conductive region disposed on the metal layer and in vertical alignment with a third region of the semiconductor layer. The third region differs from the first region and is offset from the ohmic contact layer at the first region. The offset is configured to extend an operational lifetime of the interconnection apparatus, particularly when the interconnection apparatus is exposed to high temperature environments.

VERTICAL NANORIBBON ARRAY (VERNA) THERMAL INTERFACE MATERIALS WITH ENHANCED THERMAL TRANSPORT PROPERTIES
20180342405 · 2018-11-29 ·

A thermal interface material (TIM) and method for manufacture is disclosed. A vertically aligned carbon nanotube (VACNT) array is formed on a substrate, then individual CNTs are cleaved to form a vertical nanoribbon array (VERNA). An array of aligned, upright, flat, highly-compliant ribbon elements permit a higher packing density, better ribbon-to-ribbon engagement factor, better contact with adjoining surfaces and potentially achievement of theoretical thermal conductance limit (1 GW/m2K) for such nanostructured polycyclic carbon materials. Methods for forming the VERNA include either or both of electrochemical and gas phase processing steps.

Bonding wire for semiconductor device

A bonding wire includes a Cu alloy core material, and a Pd coating layer formed on the Cu alloy core material. The bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir, and Pt. A concentration of the elements in total relative to the entire wire is 0.03% by mass or more and 2% by mass or less. When measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire axis direction has a proportion of 50% or more among crystal orientations in the wire axis direction. An average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 m or more and 1.3 m or less.