The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.

A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.

A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

An electrode is disposed on a semiconductor layer. A polyimide layer has an opening disposed on the electrode, covers the edge of the electrode, and extends onto the electrode. A copper layer is disposed on the electrode within the opening, and located away from the polyimide layer on the electrode. A copper wire has one end joined on the copper layer.

An electronic product includes a substrate and a bonding pad structure. The bonding pad structure is disposed on the substrate, and the bonding pad structure includes a first metal layer, a first insulating layer, at least one first connecting hole and a transparent conductive layer. The first metal layer and the first insulating layer are disposed on the substrate. The first connecting hole is situated in the first insulating layer, and the first connecting hole exposes a portion of the first metal layer. The transparent conductive layer is disposed on the first insulating layer, and the transparent conductive layer has a first edge and a second edge opposite to the first edge, wherein the transparent conductive layer is electrically connected to the first metal layer through the first connecting hole. A spacing between the first edge and the first connecting hole is greater than or equal to 100 m.

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.

A method for manufacturing chip package is disclosed. The method includes providing a wafer having an upper surface and a lower surface opposite thereto, in which the wafer comprises a plurality of conductive pads disposed on the upper surface; dicing the upper surface of the wafer to form a plurality of trenches; forming a patterned photoresist layer on the upper surface and in the trenches; forming a plurality of conductive bumps disposed correspondingly on the conductive pads; thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface; forming an insulating layer under the lower surface; and dicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages.

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.