Features such as bumps, pillars and/or vias can be plated best using current with either a square wave or square wave with open circuit wave form. Using the square wave or square wave with open circuit wave forms of plating current, produces features such as bumps, pillars, and vias with optimum shape and filling characteristics. Specifically, vias are filled uniformly and completely, and pillars are formed without rounded tops, bullet shape, or waist curves. In the process, the metalizing substrate is contacted with an electrolytic copper deposition composition. The deposition composition comprises a source of copper ions, an acid component selected from among an inorganic acid, an organic sulfonic acid, and mixtures thereof, an accelerator, a suppressor, a leveler, and chloride ions.

An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.

Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.

A method for high temperature bonding of substrates may include providing a top substrate and a bottom substrate, and positioning an insert between the substrates to form a assembly. The insert may be shaped to hold at least an amount of Sn having a low melting temperature and a gap shaped to hold at least a plurality of metal particles having a high melting temperature greater than the low melting temperature. The assembly may be heated to below the low melting temperature and held for a first period of time. The assembly may further be heated to approximately the low melting temperature and held for a period of time at a temperature equal to or greater than the low melting temperature such that the amount of Sn and the amount of metal particles form one or more intermetallic bonds. The assembly may be cooled to create a bonded assembly.

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint.

The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.

Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

[Object] To provide a semiconductor protective film capable of suppressing a warpage of a semiconductor chip without impairing productivity and reliability, a semiconductor device including this, and a composite sheet.

[Solving Means]A semiconductor protective film 10 according to an embodiment of the present invention includes a protective layer 11 formed of a non-conductive inorganic material and an adhesive layer 12 provided on one surface of the protective layer 11. The protective layer 11 includes at least a vitreous material and is typically formed of plate glass. Accordingly, a warpage of a semiconductor element as a protection target can be suppressed effectively.

A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.