A semiconductor device includes a printed circuit board having a plurality of first electrode pads on a first main surface and a plurality of second electrode pads electrically connected to at least one of the plurality of first electrode pads on a second main surface, a first chip disposed on the first main surface and having a non-volatile memory; a second chip having a third electrode pad and a control circuit configured to control an operation of the non-volatile memory, a dummy chip having a component that has a higher thermal conductivity than a substrate of the second chip, and a sealing member sealing the first, second, and dummy chips. The third electrode pad is connected to the component of the dummy chip via a first wiring, and the component of the dummy chip is connected to one of the plurality of first electrode pads via a second wiring.

The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.

The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.

The present application discloses a thinning system in package featuring an encapsulation structure in which no printed circuit board exists and comprising: a plurality of dies mounted on a top face of a copper holder and electrically connected to the plurality of data pins on the copper holder; a passive element mounted on the top face and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder and both the dies and the passive element are fixed on the top face of the copper holder through a layer of insulation adhesives; a molding compound encasing the dies and the passive element on the top face of the copper holder.

The present application discloses a thinning system in package featuring an encapsulation structure in which no printed circuit board exists and comprising: a plurality of dies mounted on a top face of a copper holder and electrically connected to the plurality of data pins on the copper holder; a passive element mounted on the top face and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder and both the dies and the passive element are fixed on the top face of the copper holder through a layer of insulation adhesives; a molding compound encasing the dies and the passive element on the top face of the copper holder.

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

A chip package structure and an electronic equipment may reduce probability of short circuit failure during chip packaging and improve chip reliability. The chip package structure includes: a chip, a substrate, and a lead; the chip is disposed above the substrate; wherein the chip includes a pin pad and a test metal key, and the lead is configured to electrically connect the pin pad and the substrate; the test metal key is disposed in an edge region of the chip that is not under the lead.

A chip package structure and an electronic equipment may reduce probability of short circuit failure during chip packaging and improve chip reliability. The chip package structure includes: a chip, a substrate, and a lead; the chip is disposed above the substrate; wherein the chip includes a pin pad and a test metal key, and the lead is configured to electrically connect the pin pad and the substrate; the test metal key is disposed in an edge region of the chip that is not under the lead.

A manufacturing method of a semiconductor device includes sealing a metal plate on which a semiconductor chip and a control IC are mounted by injecting molding resin raw material into a cavity from an inlet, filling the cavity with the molding resin raw material, and discharging excessive molding resin raw material from an outlet. In the case of the semiconductor device manufactured in this way, at least, generation of voids is reduced in an area around the semiconductor chip and the control IC. Thus, occurrence of an electrical discharge in the semiconductor device is reduced, and deterioration of the reliability of the semiconductor device is prevented.