A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core itself consists of: (a) pure silver consisting of (a1) silver in an amount in the range of from 99.99 to 100 wt.-% and (a2) further components in a total amount of from 0 to 100 wt.-ppm or (b) doped silver consisting of (b1) silver in an amount in the range of from >99.49 to 99.997 wt.-%, (b2) at least one doping element selected from the group consisting of calcium, nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount of from 30 to <5000 wt.-ppm and (b3) further components in a total amount of from 0 to 100 wt.-ppm, or (c) a silver alloy consisting of (c1) silver in an amount in the range of from 89.99 to 99.5 wt.-%, (c2) at least one alloying element selected from the group consisting of nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount in the range of from 0.5 to 10 wt.-% and (c3) further components in a total amount of from 0 to 100 wt.-ppm, or (d) a doped silver alloy consisting of (d1) silver in an amount in the range of from >89.49 to 99.497 wt.-%, (d2) at least one doping element selected from the group consisting of calcium, nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount of from 30 to <5000 wt.-ppm, (d3) at least one alloying element selected from the group consisting of nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount in the range of from 0.5 to 10 wt.-% and (d4) further components in a total amount of from 0 to 100 wt.-ppm, wherein the at least one doping element (d2) is other than the at least one alloying element (d3), wherein the individual amount of any further component is less than 30 wt.-ppm, wherein the individual amount of any doping element is at least 30 wt.-ppm, wherein all amounts in wt.-% and wt.-ppm are based on the total weight of the core, and wherein the coating layer is a double-layer comprised of a 1 to 1000 nm inner layer of gold and an adjacent 0.5 to 100 nm thick outer layer of palladium or a double-layer comprised of a 0.5 to 100 nm thick inner layer of palladium and an adjacent >200 to 1000 nm thick outer layer of gold.

An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield. The redistribution structure can comprise an RDS top surface coupled to the die bottom side. The interconnect can be coupled to the RDS bottom surface. The conductive strap can be coupled to the RDS, and can comprise a strap inner end coupled to the RDS bottom surface, and a strap outer end located lower than the RDS bottom surface. The encapsulant can encapsulate the conductive strap and the RDS bottom surface. The EMI shield can cover and contact the encapsulant sidewall and the strap outer end. Other examples and related methods are also disclosed herein.

An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield. The redistribution structure can comprise an RDS top surface coupled to the die bottom side. The interconnect can be coupled to the RDS bottom surface. The conductive strap can be coupled to the RDS, and can comprise a strap inner end coupled to the RDS bottom surface, and a strap outer end located lower than the RDS bottom surface. The encapsulant can encapsulate the conductive strap and the RDS bottom surface. The EMI shield can cover and contact the encapsulant sidewall and the strap outer end. Other examples and related methods are also disclosed herein.

A semiconductor device includes a semiconductor chip and a package. The semiconductor chip includes a signal processing circuit, a plurality of pads, and a first resistor which arc formed on a semiconductor substrate. On the semiconductor chip, there is no shot-circuiting between a first pad and a second pad of the plurality of pads. A signal input terminal of the signal processing circuit is connected to the second pad. The first resistor is provided between a reference potential supply terminal for supplying a power supply potential and the first pad. A specific terminal of the plurality of terminals of the package is connected to the first pad by a first bonding wire, and is connected to the second pad by a second bonding wire.

A semiconductor device includes a semiconductor chip and a package. The semiconductor chip includes a signal processing circuit, a plurality of pads, and a first resistor which arc formed on a semiconductor substrate. On the semiconductor chip, there is no shot-circuiting between a first pad and a second pad of the plurality of pads. A signal input terminal of the signal processing circuit is connected to the second pad. The first resistor is provided between a reference potential supply terminal for supplying a power supply potential and the first pad. A specific terminal of the plurality of terminals of the package is connected to the first pad by a first bonding wire, and is connected to the second pad by a second bonding wire.

The present disclosure relates to segmented shielding using wirebonds. In an exemplary aspect, a shield is formed from a series of wires (e.g., wirebonds) to create a wall and/or shielded compartment in an integrated circuit (IC) module. The wires can be located in any area within the IC module. The IC module may be overmolded with an insulating mold compound, and a top surface of the insulating mold can be ground or otherwise removed to expose ends of the wires to a shield layer which surrounds the insulating mold. Some examples may further laser ablate or otherwise form cavities around the ends of the wires to create stronger bonding between the wires of the shield and the shield layer.

The present disclosure relates to segmented shielding using wirebonds. In an exemplary aspect, a shield is formed from a series of wires (e.g., wirebonds) to create a wall and/or shielded compartment in an integrated circuit (IC) module. The wires can be located in any area within the IC module. The IC module may be overmolded with an insulating mold compound, and a top surface of the insulating mold can be ground or otherwise removed to expose ends of the wires to a shield layer which surrounds the insulating mold. Some examples may further laser ablate or otherwise form cavities around the ends of the wires to create stronger bonding between the wires of the shield and the shield layer.

In one example, a semiconductor structure or device comprises a substrate comprising a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure, an electronic component on the top side of the conductive structure, a package body on the top side of the conductive structure and contacting a side of the electronic component, a shield on a top side of the package body and a lateral side of the package body, and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure. Other examples and related methods are also disclosed herein.

In one example, a semiconductor structure or device comprises a substrate comprising a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure, an electronic component on the top side of the conductive structure, a package body on the top side of the conductive structure and contacting a side of the electronic component, a shield on a top side of the package body and a lateral side of the package body, and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure. Other examples and related methods are also disclosed herein.

A capillary for performing ball bonding includes a body defining a lumen, a first blade defined in a lower tip of the body, and a second blade defined in the lower tip of the body for increasing reliability of a ball bonding procedure performed using the capillary.