Patent classifications
H01L2924/20751
WIRE BONDING TOOL
A wire bonding tool includes a tool body with a tubular cavity extending through the tool body and a distal end. The distal end includes a flared opening at an end of the tubular cavity. The tool body further includes at least one protrusion at a level of the distal end.
COPPER BONDING WIRE
There is provided a copper bonding wire that exhibits a favorable bondability even when a scrub at the time of bonding is reduced. The copper bonding wire is characterized in that when a sum of percentages of Cu, Cu.sub.2O, CuO and Cu(OH).sub.2 on a surface of the wire as measured by X-ray Photoelectron Spectroscopy (XPS) is defined as 100%, Cu[II]/Cu[I] which is a ratio of a total percentage of CuO and Cu(OH).sub.2 (Cu[II]) corresponding to bivalent Cu to a percentage of Cu.sub.2O (Cu[I]) corresponding to monovalent Cu falls within a range from 0.8 to 12.
COPPER BONDING WIRE
There is provided a copper bonding wire that exhibits a favorable bondability even when a scrub at the time of bonding is reduced. The copper bonding wire is characterized in that when a sum of percentages of Cu, Cu.sub.2O, CuO and Cu(OH).sub.2 on a surface of the wire as measured by X-ray Photoelectron Spectroscopy (XPS) is defined as 100%, Cu[II]/Cu[I] which is a ratio of a total percentage of CuO and Cu(OH).sub.2 (Cu[II]) corresponding to bivalent Cu to a percentage of Cu.sub.2O (Cu[I]) corresponding to monovalent Cu falls within a range from 0.8 to 12.
Ag ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE
There is provided an Ag alloy bonding wire for semiconductor devices which exhibits a favorable bond reliability in a high-temperature environment even when using a mold resin of high S content and can suppress a chip damage at the time of ball bonding. The Ag alloy bonding wire is characterized by containing at least one element selected from the group consisting of Pd and Pt (hereinafter referred to as a “first element”) and at least one element selected from the group consisting of P, Cr, Zr and Mo (hereinafter referred to as a “second element”) so as to satisfy
where x1 is a total concentration of the first element [at.%] and x2 is a total concentration of the second element [at. ppm], with the balance including Ag.
Ag ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE
There is provided an Ag alloy bonding wire for semiconductor devices which exhibits a favorable bond reliability in a high-temperature environment even when using a mold resin of high S content and can suppress a chip damage at the time of ball bonding. The Ag alloy bonding wire is characterized by containing at least one element selected from the group consisting of Pd and Pt (hereinafter referred to as a “first element”) and at least one element selected from the group consisting of P, Cr, Zr and Mo (hereinafter referred to as a “second element”) so as to satisfy
where x1 is a total concentration of the first element [at.%] and x2 is a total concentration of the second element [at. ppm], with the balance including Ag.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
A method includes providing a substrate having substrate terminals and providing a first component having a first terminal and a second terminal. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first terminal and a substrate terminal and coupling the second clip to another substrate terminal. The method includes encapsulating the structure and removing a portion of the clip connector. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant. Other examples and related structures are also disclosed herein.
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
A method includes providing a substrate having substrate terminals and providing a first component having a first terminal and a second terminal. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first terminal and a substrate terminal and coupling the second clip to another substrate terminal. The method includes encapsulating the structure and removing a portion of the clip connector. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant. Other examples and related structures are also disclosed herein.
SEMICONDUCTOR DEVICES INCLUDING SHIELDING LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
In one example, a semiconductor structure or device comprises a substrate comprising a conductive structure having a top side and a first shielding terminal on the top side of the conductive structure, an electronic component on the top side of the conductive structure, a package body on the top side of the conductive structure and contacting a side of the electronic component, a shield on a top side of the package body and a lateral side of the package body, and a shield interconnect coupling the shield to the first shielding terminal of the conductive structure. Other examples and related methods are also disclosed herein.