A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

To provide a semiconductor light emitting device which is capable of accomplishing a broad color reproducibility for an entire image without losing brightness of the entire image. A light source provided on a backlight for a color image display device has a semiconductor light emitting device comprising a solid light emitting device to emit light in a blue or deep blue region or in an ultraviolet region and phosphors, in combination. The phosphors comprise a green emitting phosphor and a red emitting phosphor. The green emitting phosphor and the red emitting phosphor are ones, of which the rate of change of the emission peak intensity at 100° C. to the emission intensity at 25° C., when the wavelength of the excitation light is 400 nm or 455 nm, is at most 40%.

To provide a semiconductor light emitting device which is capable of accomplishing a broad color reproducibility for an entire image without losing brightness of the entire image. A light source provided on a backlight for a color image display device has a semiconductor light emitting device comprising a solid light emitting device to emit light in a blue or deep blue region or in an ultraviolet region and phosphors, in combination. The phosphors comprise a green emitting phosphor and a red emitting phosphor. The green emitting phosphor and the red emitting phosphor are ones, of which the rate of change of the emission peak intensity at 100° C. to the emission intensity at 25° C., when the wavelength of the excitation light is 400 nm or 455 nm, is at most 40%.

In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.

In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.

In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

An object of the present invention is to provide an Ag alloy bonding wire for a semiconductor device capable of extending the high-temperature life of a wire, reducing chip damage during ball bonding, and improving characteristics such as ball bonding strength in applications of on-vehicle memory devices. The Ag alloy bonding wire for a semiconductor device according to the present invention contains one or more of In and Ga for a total of 110 at ppm or more and less than 500 at ppm, and one or more of Pd and Pt for a total of 150 at ppm or more and less than 12,000 at ppm, and a balance being made up of Ag and unavoidable impurities.

An object of the present invention is to provide an Ag alloy bonding wire for a semiconductor device capable of extending the high-temperature life of a wire, reducing chip damage during ball bonding, and improving characteristics such as ball bonding strength in applications of on-vehicle memory devices. The Ag alloy bonding wire for a semiconductor device according to the present invention contains one or more of In and Ga for a total of 110 at ppm or more and less than 500 at ppm, and one or more of Pd and Pt for a total of 150 at ppm or more and less than 12,000 at ppm, and a balance being made up of Ag and unavoidable impurities.

In examples, an electronic device comprises a printed circuit board (PCB), an orifice extending through the PCB, and a semiconductor die suspended above the orifice by aluminum bond wires. The semiconductor die is vertically aligned with the orifice and the bond wires coupled to the PCB.