A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.

A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.

A solder ball includes a silver ball structure and a shell structure. The shell structure wraps a surface of the silver ball structure, and a material of the shell structure at least includes tin. When the solder ball is bonded to other devices, the ball height of the solder ball remains constant to avoid collapse.

A semiconductor device has a module structure in which a semiconductor element and a circuit layer are electrically connected to each other by a wire. A front metal layer is formed on a surface of a top side electrode of the semiconductor element and the wire is bonded to the front metal layer by wire bonding. The front metal layer has a higher hardness than the top side electrode or the wire. A bonding interface of the wire with the metal film has a recrystallization temperature that is equal to or higher than 175° C. According to this structure, it is possible to improve the power cycle resistance of the semiconductor device.