Patent classifications
H01L2924/20756
Solder ball, manufacturing method thereof, and semiconductor device
A solder ball includes a silver ball structure and a shell structure. The shell structure wraps a surface of the silver ball structure, and a material of the shell structure at least includes tin. When the solder ball is bonded to other devices, the ball height of the solder ball remains constant to avoid collapse.
Semiconductor device and method for manufacturing the semiconductor device
A semiconductor device has a module structure in which a semiconductor element and a circuit layer are electrically connected to each other by a wire. A front metal layer is formed on a surface of a top side electrode of the semiconductor element and the wire is bonded to the front metal layer by wire bonding. The front metal layer has a higher hardness than the top side electrode or the wire. A bonding interface of the wire with the metal film has a recrystallization temperature that is equal to or higher than 175° C. According to this structure, it is possible to improve the power cycle resistance of the semiconductor device.
Semiconductor device and method for manufacturing the semiconductor device
A semiconductor device has a module structure in which a semiconductor element and a circuit layer are electrically connected to each other by a wire. A front metal layer is formed on a surface of a top side electrode of the semiconductor element and the wire is bonded to the front metal layer by wire bonding. The front metal layer has a higher hardness than the top side electrode or the wire. A bonding interface of the wire with the metal film has a recrystallization temperature that is equal to or higher than 175° C. According to this structure, it is possible to improve the power cycle resistance of the semiconductor device.
PROCESS FOR ELECTRICALLY CONNECTING CONTACT SURFACES OF ELECTRONIC COMPONENTS
A process for electrically connecting contact surfaces of electronic components by capillary wedge bonding a round wire of 8 to 80 μm to the contact surface of a first electronic component, forming a wire loop, and stitch bonding the wire to the contact surface of a second electronic component, wherein the wire comprises a wire core having a silver or silver-based wire core with a double-layered coating comprised of a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold.
PROCESS FOR ELECTRICALLY CONNECTING CONTACT SURFACES OF ELECTRONIC COMPONENTS
A process for electrically connecting contact surfaces of electronic components by capillary wedge bonding a round wire of 8 to 80 μm to the contact surface of a first electronic component, forming a wire loop, and stitch bonding the wire to the contact surface of a second electronic component, wherein the wire comprises a wire core having a silver or silver-based wire core with a double-layered coating comprised of a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold.
Device including multiple semiconductor chips and multiple carriers
A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.
Device including multiple semiconductor chips and multiple carriers
A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.
DIE-TO-DIE ISOLATION STRUCTURES FOR PACKAGED TRANSISTOR DEVICES
A transistor amplifier package includes a base, one or more transistor dies on the base, first and second leads coupled to the one or more transistor dies and defining respective radio frequency (RF) signal paths, and an isolation structure on the base between the respective RF signal paths. The isolation structure includes first and second wire bonds. The first and second wire bonds may have a crossed configuration defining at least one cross point therebetween. Related wire bond-based isolation structures are also discussed.
DIE-TO-DIE ISOLATION STRUCTURES FOR PACKAGED TRANSISTOR DEVICES
A transistor amplifier package includes a base, one or more transistor dies on the base, first and second leads coupled to the one or more transistor dies and defining respective radio frequency (RF) signal paths, and an isolation structure on the base between the respective RF signal paths. The isolation structure includes first and second wire bonds. The first and second wire bonds may have a crossed configuration defining at least one cross point therebetween. Related wire bond-based isolation structures are also discussed.
Multiple bond via arrays of different wire heights on a same substrate
An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.