Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A semiconductor device that includes a plurality of trench gate structures each having a gate electrode extending in a depth direction of an element, the plurality of trench gate structures including first trench gate structures respectively contributing to control of the element and second trench gate structures respectively not contributing to the control of the element, the semiconductor device including an electrode portion having a potential other than a gate potential, and an electrode pad that is disposed on a front face of a semiconductor substrate, wherein the electrode pad is used as a terminal to apply a predetermined voltage to gate insulator films, in screening that is executed by applying the predetermined voltage to the gate insulator films respectively in contact with the gate electrode connected to the electrode pad and that is executed before the electrode pad is short-circuited to the electrode portion.

A semiconductor device that includes a plurality of trench gate structures each having a gate electrode extending in a depth direction of an element, the plurality of trench gate structures including first trench gate structures respectively contributing to control of the element and second trench gate structures respectively not contributing to the control of the element, the semiconductor device including an electrode portion having a potential other than a gate potential, and an electrode pad that is disposed on a front face of a semiconductor substrate, wherein the electrode pad is used as a terminal to apply a predetermined voltage to gate insulator films, in screening that is executed by applying the predetermined voltage to the gate insulator films respectively in contact with the gate electrode connected to the electrode pad and that is executed before the electrode pad is short-circuited to the electrode portion.

A bonding wire and a method of manufacturing the bonding wire are provided. The bonding wire contains 90.0 to 99.0 wt % of silver (Ag); 0.2 to 2.0 wt % of gold (Au); 0.2 to 4.0 wt % of palladium (Pd), platinum (Pt), rhodium (Rh), or a combination thereof; 10 to 1000 ppm of dopants; and inevitable impurities. In the wire, the ratio of (a)/(b) is 3 to 5, in which (a) represents the amount of crystal grains having <100> orientation in crystalline orientations <hkl> in a wire lengthwise direction and (b) represents the amount of crystal grains having <111> orientation in crystalline orientations <hkl> in the wire lengthwise direction.

A bonding wire and a method of manufacturing the bonding wire are provided. The bonding wire contains 90.0 to 99.0 wt % of silver (Ag); 0.2 to 2.0 wt % of gold (Au); 0.2 to 4.0 wt % of palladium (Pd), platinum (Pt), rhodium (Rh), or a combination thereof; 10 to 1000 ppm of dopants; and inevitable impurities. In the wire, the ratio of (a)/(b) is 3 to 5, in which (a) represents the amount of crystal grains having <100> orientation in crystalline orientations <hkl> in a wire lengthwise direction and (b) represents the amount of crystal grains having <111> orientation in crystalline orientations <hkl> in the wire lengthwise direction.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

There is provided an Al bonding wire which can provide a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the Al bonding wire is operated. The bonding wire is composed of Al or Al alloy, and is characterized in that an average crystal grain size in a cross-section of a core wire in a direction perpendicular to a wire axis of the bonding wire is 0.01 to 50 μm, and when measuring crystal orientations on the cross-section of the core wire in the direction perpendicular to the wire axis of the bonding wire, a crystal orientation <111> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30 to 90% among crystal orientations in the wire longitudinal direction.