Disclosed is a display driving device including a bonding resistance measurement circuit. The display driving device may include: first and second pads bonded to a pad of a display panel through a wire and configured to provide bonding resistance; and a bonding resistance measurement circuit configured to measure the bonding resistance by comparing an input voltage applied to the bonding resistance through the first pad to one or more preset reference voltages.

A semiconductor device includes a substrate, a semiconductor die, and an antistatic die attach material between the substrate and the semiconductor die. The antistatic die attach material includes a mixture of a nonconductive adhesive material and carbon black or graphite. In one example, the antistatic die attach material has a resistivity between 10.sup.1 Ω.Math.cm and 10.sup.10 Ω.Math.cm.

An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

A tiled light emitting diode (LED) display panel includes multiple flexible back plates arranged in tiles. Each flexible back plate has multiple through holes formed thereon. A pixel array is formed by multiple LEDs on the flexible back plates and collectively defines multiple pixels. Each pixel includes one LED and thin-film transistor (TFT) circuits disposed on a first side of a corresponding flexible back plate. A printed circuit board (PCB) is disposed at a second side of the flexible back plates. A third side of the PCB faces the second side of the flexible back plates and has multiple signal lines formed thereon. The LEDs and the TFT circuits of the pixels are electrically connected to the corresponding signal lines via multiple conductive structures formed in the through holes. A resistance per unit length of each flexible back plates is greater than a resistance per unit length of the PCB.

A tiled light emitting diode (LED) display panel includes multiple flexible back plates arranged in tiles. Each flexible back plate has multiple through holes formed thereon. A pixel array is formed by multiple LEDs on the flexible back plates and collectively defines multiple pixels. Each pixel includes one LED and thin-film transistor (TFT) circuits disposed on a first side of a corresponding flexible back plate. A printed circuit board (PCB) is disposed at a second side of the flexible back plates. A third side of the PCB faces the second side of the flexible back plates and has multiple signal lines formed thereon. The LEDs and the TFT circuits of the pixels are electrically connected to the corresponding signal lines via multiple conductive structures formed in the through holes. A resistance per unit length of each flexible back plates is greater than a resistance per unit length of the PCB.

A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.

A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.

A semiconductor module includes: a first metal plate including a first mount part joined with a bottom-surface electrode of a first switching element, a second mount part joined with a positive-electrode terminal, and a first narrow part between the first and second mount parts and being narrower than a part jointing the first switching element to the first mount part and the positive-electrode terminal; a second metal plate being joined with a bottom-surface electrode of a second switching element, and connected to a top-surface electrode of the first switching element; a third metal plate including a sixth mount part joined with a negative-electrode terminal, a seventh mount part connected to a top-surface electrode of the second switching element, and being narrower than the negative-electrode terminal, and a second narrow part between the sixth and seventh mount parts; and a snubber circuit connecting the first and second narrow parts.

A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.

A wafer level chip scale package includes a semiconductor substrate having a first thickness, an input-output pad formed on the semiconductor substrate, a front metal layer having a second thickness formed on the input-output pad, a back metal layer having a third thickness formed on a bottom of the semiconductor substrate, and a metal bump formed on the semiconductor substrate.