A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.

A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate. The method also includes attaching an electronic component to the substrate. The method further includes attaching a fixing feature to an upper surface of the electronic component. In addition, the method includes forming a bonding wire connecting the substrate and the electronic component. The bonding wire is at least partially disposed on the fixing feature.

An electronic device includes an electronic unit, a circuit layer and a bonding pad. The electronic unit includes a chip, an insulating layer and a first conductor layer. The insulating layer is disposed on the chip, the insulating layer includes a first opening, and the first conductor layer is disposed in the first opening. The circuit layer is disposed corresponding to the electronic unit, and the circuit layer includes a second opening and a second conductor layer disposed in the second opening. The bonding pad is in contact with the second conductor layer, and the bonding pad is electrically connected to electronic unit. The first conductor layer has a first height, the second conductor layer has a second height, and a ratio of the first height to the second height is greater than or equal to 0.1 and less than or equal to 0.9.

A semiconductor device includes a semiconductor element, a terminal electrode, and internal wiring. The semiconductor element is housed in a case. The terminal electrode is provided electrically connectable to an outside of the case. The internal wiring is provided in the case and electrically connects the semiconductor element and the terminal electrode. The internal wiring includes a fuse portion provided at a part of the internal wiring and configured to be melted by an overcurrent. The fuse portion includes a plurality of metal wires which are a group of parallel wires. Of the plurality of metal wires, a first metal wire is higher in resistance value than a second metal wire laid on an outer side relative to the first metal wire.

A packaged circuit system structure with circuit elements embedded into a bulk material. At least one of the embedded circuit elements forms a dual coupling that includes an electrical connection to a signal ground potential on one side of the structure and an electrical connection to a conductive layer on the other side of the structure. The conductive layer extends over at least one embedded circuit element that does not form a dual coupling, and thereby provides an effective EMI shielding for it.

A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.

In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 510.sup.6/ C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.