There are disclosed impedance matching networks and technique for impedance matching to microwave power transistors. Distributed capacitor inductor networks are used so as to provide a high degree of control and accuracy, especially in terms of inductance values, in comparison to existing lumped capacitor arrangements. The use of bond wires is reduced, with inductance being provided primarily by microstrip transmission lines on the capacitors.

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.

In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.

The embodiments described herein provide an amplifier device that utilizes bonding pad capacitance in an impedance matching network. In one specific embodiment, the amplifier device comprises: an amplifier formed on a semiconductor die, the amplifier including an amplifier input and an amplifier output, the amplifier configured to generate an amplified radio frequency (RF) signal at the amplifier output; and an impedance matching network coupled to the amplifier, the impedance matching network including a capacitor, where the capacitor includes a first plate, a second plate, and dielectric material between the first and second plates, where the first plate includes or is directly electrically coupled to a bond pad on the semiconductor die.

Low inductance to ground can be provided in wire-bond based device packages. An example device package may include a die on a package substrate, a mold on the package substrate and encapsulating the die, an upper ground conductor on the mold, and ground wire bonds within the mold. The die may include a plurality of terminals on an upper surface of the die. The plurality of ground wire bonds may electrically couple the die and the upper ground conductor. For each ground wire bond, a first end of that ground wire bond may be configured to electrically couple to a corresponding terminal on the upper surface of the die and a second end of that ground wire bond may be configured to electrically couple to the upper ground conductor at the upper surface of the mold.

In general, according to one embodiment, a semiconductor device includes a device main body, a semiconductor substrate. The device main body includes a semiconductor substrate mounting part and a first conductor provided around the semiconductor substrate mounting part. The semiconductor substrate includes a DC-to-DC converter control circuit having a detector to detect at least one of a current flowing through the first conductor and a voltage supplied to the first conductor. The semiconductor substrate is disposed on the semiconductor substrate mounting part so that the detector comes close to the first conductor.

In general, according to one embodiment, a semiconductor device includes a device main body, a semiconductor substrate. The device main body includes a semiconductor substrate mounting part and a first conductor provided around the semiconductor substrate mounting part. The semiconductor substrate includes a DC-to-DC converter control circuit having a detector to detect at least one of a current flowing through the first conductor and a voltage supplied to the first conductor. The semiconductor substrate is disposed on the semiconductor substrate mounting part so that the detector comes close to the first conductor.

A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.