Monolithic pixel detectors, systems and methods for the detection and imaging of radiation in the form of energetic particles which may have a mass or be massless (such as X-ray photons) comprise a Si wafer with a CMOS processed readout communicating via implants for charge collection with an absorber forming a monolithic unit with the Si wafer to collect and process the electrical signals generated by radiation incident on the absorber. The pixel detectors, systems and methods are used in various medical, industrial and scientific types of applications.

A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.

A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.

The present disclosure discloses a trench Insulated Gate Bipolar Transistor (IGBT) packaging structure and a method for manufacturing the trench Insulated Gate Bipolar Transistor packaging structure. The trench IGBT packaging structure includes: a trench IGBT, which includes an emitting electrode metal layer, and a trench gate electrode; a lead frame, which includes a chip placement area and an emitting electrode lead-out end; a first bonding wire connecting the emitting electrode metal layer and an emitting electrode pin. One end of the first bonding wire is connected to a surface, away from the trench gate electrode, of the emitting electrode metal layer to form a strip-shaped first solder joint, the other end is connected to the emitting electrode lead-out end to form a second solder joint, and an extension direction of the first solder joint is perpendicular to an extension direction of the trench of the trench gate electrode.

A semiconductor device having an electrode type of the ball grid array (BGA) and a process of forming the electrode are disclosed. The electrode insulating film, a seed layer on the insulating film, a mound metal on the insulating film and an interconnection on the seed layer. The mound metal surrounds the seed layer without forming any gap therebetween. The interconnection, which is formed by electroless plating, is apart from the insulating film with the mound metal as an extension barrier for the plating.

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.

Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.