A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.

A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.

A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, and a first chip connection structure disposed between the first semiconductor chip and the second semiconductor chip. The first chip connection structure includes a first insertion connection structure connected to the first semiconductor chip, a first recess connection structure connected to the second semiconductor chip, and a first contact layer interposed between the first insertion connection structure and the first recess connection structure. The first recess connection structure includes a base and a side wall which defines a recess. A portion of the first insertion connection structure is disposed in the recess. A portion of the first contact layer is disposed in the recess, and the first contact layer covers at least a portion of a bottom surface of the side wall.

A described example includes: a MEMS component on a device side surface of a first semiconductor substrate; a second semiconductor substrate bonded to the device side surface of the first semiconductor substrate by a first seal patterned to form sidewalls that surround the MEMS component; a third semiconductor substrate having a second seal extending from a surface and bonded to the backside surface of the first semiconductor substrate by the second seal, the second seal forming sidewalls of a gap beneath the MEMS component. A trench extends through the first semiconductor substrate and at least partially surrounds the MEMS component. The third semiconductor substrate is mounted on a package substrate. A bond wire or ribbon bond couples the bond pad to a conductive lead on the package substrate; and mold compound covers the MEMS component, the bond wire, and a portion of the package substrate.

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

An object of the present technology is to prevent damage in a bonded portion between a semiconductor chip and a substrate in a semiconductor device in which the semiconductor chip is mounted on the substrate.

A terminal is disposed between an electrode of an element and an electrode of a substrate on which the element is mounted, and electrically connects the electrode of the element and the electrode of the substrate. The terminal includes a plurality of unit lattices and a coupling portion. The unit lattices included in the terminal are formed by bonding a plurality of beams in a cube shape. The coupling portion included in the terminal couples adjacent unit lattices among the plurality of unit lattices.