A flip chip bonding method includes obtaining a die including a first substrate and an adhesive layer on the first substrate; bonding the die to a second substrate different from the first substrate; and curing the adhesive layer. The curing the adhesive layer includes heating the second substrate to melt the adhesive layer, and providing the adhesive layer and the second substrate with air having pressure greater than atmospheric pressure.

An adhesion layer may be formed over portions of a redistribution layer (RDL) in a redistribution structure of a semiconductor device package. The portions of the RDL over which the adhesion layer is formed may be located in the shadow of (e.g., the areas under and/or over and within the perimeter of) one or more TIVs that are connected with the redistribution layer structure. The adhesion layer, along with a seed layer on which the portions of the RDL are formed, encapsulate the portions of the RDL in the shadow of the one or more TIVs, which promotes and/or increases adhesion between the portions of the RDL and the polymer layers of the redistribution structure.

An electronic device package may include a solder mask that is positioned to mitigate leakage of resin or other adhesive material from the region of a die and die bond pad onto other surfaces of the package, such as surfaces of wire bond pads. One or more wire bond pads of the package may be formed from the same conductive layer as the die bond pad, and the solder mask may be positioned over a portions of the conductive layer located directly between such wire bond pads and the die bond pad. The solder mask may include portions disposed at one or more sides of the die bond pad. The solder mask may be formed over the package substrate prior to attachment of the die to the die bond pad.

A method for manufacturing a semiconductor device and an underfill film which can achieve voidless mounting and excellent solder bonding properties even in the case of collectively bonding a plurality of semiconductor chips are provided. The method includes a mounting step of mounting a plurality of semiconductor chips having a solder-tipped electrode onto an electronic component having a counter electrode opposing the solder-tipped electrode via an underfill film; and a compression bonding step of collectively bonding the plurality of semiconductor chips to the electronic component via the underfill film. The underfill film contains an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide and has a minimum melt viscosity of 1,000 to 2,000 Pa*s and a melt viscosity gradient of 900 to 3,100 Pa*s/ C. from a temperature 10 C. higher than a minimum melt viscosity attainment temperature to a temperature 10 C. higher than the temperature.

A semiconductor structure includes a substrate; a post passivation interconnect (PPI) disposed over the substrate and including a plurality of first elongated members extended over a surface of the substrate and a plurality of second elongated members extended over the surface of the substrate and isolated from the plurality of first elongated members; a first polymeric layer covering the PPI; and a second polymeric layer disposed over the first polymeric layer, wherein the plurality of first elongated members are alternately disposed with the plurality of second elongated members, the first polymeric layer includes a recessed portion disposed between one of the plurality of first elongated members and one of the plurality of second elongated members, and the second polymeric layer includes a protruded portion disposed within the recessed portion.

A method for manufacturing a semiconductor device and an underfill film which can achieve voidless mounting and excellent solder bonding properties even in the case of collectively bonding a plurality of semiconductor chips are provided. The method includes a mounting step of mounting a plurality of semiconductor chips having a solder-tipped electrode onto an electronic component having a counter electrode opposing the solder-tipped electrode via an underfill film; and a compression bonding step of collectively bonding the plurality of semiconductor chips to the electronic component via the underfill film. The underfill film contains an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide and has a minimum melt viscosity of 1,000 to 2,000 Pa*s and a melt viscosity gradient of 900 to 3,100 Pa*s/ C. from a temperature 10 C. higher than a minimum melt viscosity attainment temperature to a temperature 10 C. higher than the temperature.

A semiconductor structure and a method of forming the same are disclosed. A method of forming a semiconductor structure includes the following operations. An insulating layer is formed over a substrate. A metal feature is formed in the insulating layer. An argon-containing plasma treatment is performed to the insulating layer and the metal feature.

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

A semiconductor structure includes a substrate; a post passivation interconnect (PPI) disposed over the substrate and including a plurality of first elongated members extended over a surface of the substrate and a plurality of second elongated members extended over the surface of the substrate and isolated from the plurality of first elongated members; a first polymeric layer covering the PPI; and a second polymeric layer disposed over the first polymeric layer, wherein the plurality of first elongated members are alternately disposed with the plurality of second elongated members, the first polymeric layer includes a recessed portion disposed between one of the plurality of first elongated members and one of the plurality of second elongated members, and the second polymeric layer includes a protruded portion disposed within the recessed portion.

An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.