Provided is a method of fabricating a package including: providing a die with a contact thereon; forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising: forming a first dielectric material on the die; forming a conductive feature in and partially on the first dielectric material; after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers a top surface of the conductive feature and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to expose the conductive feature; and forming a plurality of conductive connectors to electrically connect the die through the RDL structure.

Provided is a package including a die, a redistribution layer (RDL) structure, and a plurality of conductive connectors. The RDL structure includes a dielectric layer, a conductive feature, and a protective layer. The conductive feature is disposed in the dielectric layer and electrically connected to the die. The protective layer is disposed between the dielectric layer and the conductive feature. The protective layer, the dielectric layer, and the conductive feature have different materials. The plurality of conductive connectors are electrically connected to the die through the RDL structure.

A semiconductor device, including a semiconductor chip having a first main electrode on a front surface thereof, the first main electrode having a plurality of bonded regions, and a plurality of wires that are bonded respectively to the plurality of bonded regions of the first main electrode. In a top view of the semiconductor device, the plurality of bonded regions do not overlap in either a predetermined first direction, or a second direction perpendicular to the predetermined first direction.

Provided is a package including a die, a redistribution layer (RDL) structure, and a plurality of conductive connectors. The RDL structure includes a dielectric layer, a conductive feature, and a protective layer. The conductive feature is disposed in the dielectric layer and electrically connected to the die. The protective layer is disposed between the dielectric layer and the conductive feature. The protective layer, the dielectric layer, and the conductive feature have different materials. The plurality of conductive connectors are electrically connected to the die through the RDL structure.

A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type on a substrate of the first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a first semiconductor region of the first conductivity type. The semiconductor device further includes a gate electrode provided in a plurality of trenches via gate insulating films, a protruding portion disposed on the second semiconductor layer at a bridge area between two adjacent ones of the trenches in a direction orthogonal to the trenches, an interlayer insulating film provided on the gate electrode, and having contact holes that form a striped pattern, a first electrode on the interlayer insulating film and in the contact holes, a plating film provided in a plating area, and a solder on the plating film.

A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess.

In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a resist layer disposed on a conductive layer. The semiconductor package also has a bump disposed on the conductive layer. The bump has a top surface and one or more sidewalls. The semiconductor package further includes a surface finish disposed on the top surface and the one or more sidewalls of the bump. The semiconductor package may have the surface finish surround the top surface and sidewalls of the bumps to protect the bumps from Galvanic corrosion. The surface finish may include a nickel-palladium-gold (NiPdAu) surface finish. The semiconductor package may also have a seed disposed on a top surface of the resist layer, and a dielectric disposed on the seed. The dielectric may surround the sidewalls of the bump. The semiconductor package may include the seed to be an electroless copper seed.

Provided is a method of fabricating a package including: providing a die with a contact thereon; forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising: forming a first dielectric material on the die; forming a conductive feature in and partially on the first dielectric material; after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers a top surface of the conductive feature and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to expose the conductive feature; and forming a plurality of conductive connectors to electrically connect the die through the RDL structure.

A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.