A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.

A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.

In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.

A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure laterally surrounding the first conductive structure; and an underfill material, partially surrounding the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the underfill material.

A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.

A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.

The present disclosure provides a package device including a conductive pad, a protecting block, and a redistribution layer. The protecting block is disposed on the conductive pad. The redistribution layer is disposed on the protecting block, and the conductive pad is electrically connected to the redistribution layer through the protecting block.

A light emitting diode includes: a light emitting layer arranged on at least part of a first semiconductor layer, and a second semiconductor layer; a local defect region over a portion of the second semiconductor layer and extending downward to the first semiconductor layer; a metal layer over a portion of the second semiconductor layer; an insulating layer covering the metal layer, the second and first semiconductor layers in the local defect region, with opening structures over the local defect region and the metal layer, respectively; and an electrode structure over the insulating layer and having a first layer and a second layer, and including a first-type electrode region and a second-type electrode region; wherein an upper surface and a lower surface of the first layer are not flat, and a lower surface of the second layer are both flat.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip. A first conductive connection wire of the first chip is connected to a first conductive contact pad, and a second conductive connection wire of the second chip is connected to a second conductive contact pad. In addition, the first conductive contact pad includes a first conductor and a second conductor, and the second conductive contact pad includes a third conductor and a fourth conductor. The first conductor is directly opposite to the fourth conductor, and the second conductor is directly opposite to the third conductor. Therefore, pre-connection of the first conductive contact pad and the second conductive contact pad may be implemented and then the first chip and second chip that are pre-connected are transferred for bonding.