The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

A semiconductor package includes an interposer; a first stacked chip including a first semiconductor chip disposed on the interposer and one or more second semiconductor chips disposed on the first semiconductor chip; a first molding layer surrounding the first stacked chip; and a second molding layer surrounding the first molding layer, wherein the second molding layer extends from an uppermost surface of the interposer to a trench of the interposer.

A semiconductor package includes a frame having a first surface and a second surface, and including a wiring structure and a through-hole. The package further includes a first redistribution structure disposed on the first surface of the frame and including a first insulating layer and a first redistribution layer on the first insulating layer and connected to the wiring structure, a bridge die in the through-hole and having an interconnector, and an encapsulant surrounding the bridge die, and covering the second surface of the frame. The package further includes a second redistribution structure disposed on the encapsulant, and including a second insulating layer and a second redistribution layer on the second insulating layer and connected to the interconnector and the wiring structure, and a plurality of semiconductor chips disposed on the second redistribution structure, connected to the second redistribution layer, and electrically connected to each other through the interconnector.

A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

A bonded assembly includes a first semiconductor die that includes first metallic bonding structures embedded within a first bonding-level dielectric layer, and a second semiconductor die that includes second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding. One of the first metallic bonding structures a pad portion, and a via portion located between the pad portion and the first semiconductor device, the via portion having second tapered sidewalls.

A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.

Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

A semiconductor package including a semiconductor chip, and a package structure configured to accommodate the semiconductor chip, and a manufacturing method thereof are disclosed. The package structure includes a substrate having one surface and the other surface opposite to the one surface, at least one conductive via extending through one surface and the other surface of the substrate, a wiring layer formed at one surface of the substrate, to transmit an electrical signal, a chip accommodating portion formed through removal of a portion of the substrate from the other surface toward the one surface, and a contact pad connected to the wiring layer and formed to be exposed through the chip accommodating portion. The semiconductor chip is inserted into the chip accommodating portion and is connected to the contact pad. Since the semiconductor chip is mounted after formation of the package structure, yield of the semiconductor package increases.