A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.

A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

A semiconductor device may include a semiconductor substrate, a first bonding pad provided on an upper surface of the semiconductor substrate and constituted of a metal including aluminum, and a second bonding pad provided on the upper surface of the semiconductor substrate. An upper surface of the first bonding pad may be inclined such that positions on the upper surface of the first bonding pad which are closer to the second bonding pad are positioned further above.

This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

A plurality of wires of a semiconductor device includes: a first wire connected to each of an end portion electrode and a first terminal of a plurality of terminals; and a second wire connected to each of a non-end portion electrode and a second terminal of the plurality of terminals. A loop height of the first wire is greater than a loop height of the second wire.

There is provided an Al bonding wire which can provide a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the Al bonding wire is operated. The bonding wire is composed of Al or Al alloy, and is characterized in that an average crystal grain size in a cross-section of a core wire in a direction perpendicular to a wire axis of the bonding wire is 0.01 to 50 ?m, and when measuring crystal orientations on the cross-section of the core wire in the direction perpendicular to the wire axis of the bonding wire, a crystal orientation <111> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30 to 90% among crystal orientations in the wire longitudinal direction.

A method of calibrating an ultrasonic characteristic on a wire bonding system is provided. The method includes the steps of: (a) determining a reference ultrasonic characteristic for formation of a wire bond; (b) determining a reference non-stick ultrasonic characteristic that results in a non-stick wire bond condition; (c) determining a calibration non-stick ultrasonic characteristic, on a wire bonding system to be calibrated, that results in a non-stick wire bond condition; and (d) determining a calibration factor for the wire bonding system to be calibrated using the reference non-stick ultrasonic characteristic and the calibration non-stick ultrasonic characteristic.

A wiring board includes an electronic component; an insulating layer containing the electronic component therein, and including a via hole that is open at one surface of the insulating layer to expose an electrode of the electronic component; a first wiring layer embedded in the insulating layer, one surface of the first wiring layer being exposed at the one surface of the insulating layer; a second wiring layer including a wiring pattern formed on the one surface of the first wiring layer, and a via wiring extended from the wiring pattern to be extended in the via hole and directly connected to an electrode of the electronic component.

A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.

The surface of a substrate of a first material is modified by depositing a layer of a solvent paste comprising nanoparticles of a second material that have a size that provides a melting point at a lower temperature than the melting point temperature of the bulk second material, and nanoparticles of a third material that have a size at least as large as the nanoparticle size of the second material and a melting point at a temperature higher than the melting point temperature of the second material. Nanoparticles of the second material have a higher weight percentage than nanoparticles of the third material. The nanoparticles of the second material are sintered together at the melting point temperature of the second material. Voids are created in the layer of second material by removing the nanoparticles of the third material The voids have random distribution and random three-dimensional configurations.