A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

An electronic device according to various embodiments of the present invention may comprise: a circuit substrate comprising a first layer including a first wire, a second wire formed at one side surface of the first wire along the first wire, and a third wire formed at the other side surface of the first wire along the first wire, a second layer including a ground plane formed along the first wire, the second wire, and the third wire and electrically connected to the second wire and the third wire, and an insulation layer disposed between the first layer and the second layer and having first permittivity; and a conductive member which is disposed above the first layer to have a dielectric-fillable interval space along the first wire and is electrically connected to the ground of the electronic device, the dielectric having second permittivity lower than the first permittivity.

A circuit includes a first input and output terminals to which a current, a voltage, or an electromagnetic wave (referred to as “current or the like” below) is applied, a second input and output terminals to which the current or the like is applied, a first board including a matrix circuit which is formed by a first line and includes a 90-degree hybrid circuit and a delay line, the first line in which one end is connected to the first input and output terminals and a tip of the other end is opened, a second board including a second line in which one end is connected to the second input and output terminals, and a tip of the other end is opened, and a shielding plate including an opening portion.

A filtering power divider includes a first partial transmission line having a first electrical length, a second partial transmission line having a second electrical length, and a third partial transmission line having the second electrical length. The first, second, and third partial transmission lines connect to form a T-junction, and a sum of the first and second electrical lengths is ninety degrees. Thus, the first and second partial transmission lines cooperate to act as a quarter-wave transmission line. Similarly, the first and third partial transmission lines cooperate to act as a quarter-wave transmission line. Additional transmission lines may be connected to the first, second, and third partial transmission lines to implement a filter between an input port and each of two output ports.

Embodiments of a circuit, system, and method are disclosed. In an embodiment, a circuit includes first and second microstrip transmission lines. The first and second microstrip transmission lines include linearly arranged conductive strips on the circuit and a slotline formation extends between the first microstrip transmission line and the second microstrip transmission line so that the slotline formation is configured to electromagnetically couple the first microstrip transmission line to the second microstrip transmission line during operation of the circuit. In addition, the circuit includes at least one controllable capacitance circuit electrically connected to at least one of the first microstrip transmission line and the second microstrip transmission line, where a magnitude of a capacitance value of the at least one controllable capacitance circuit (e.g., including a barium strontium titanate (BST) capacitor) is controllable (e.g., in response to a capacitance control signal received at a control interface).

A waveguide microstrip line converter includes a waveguide, a dielectric substrate, a ground conductor including a slot, and a line conductor. The line conductor includes a first section that is a microstrip line having a first line width, a conversion unit that is a second section positioned immediately above the slot and having a second line width greater than the first line width, and a third section extending from the second section in a first direction and performing impedance matching between the first section and the second section. One of the opposite ends of the third section in the first direction is connected to the second section. The first section extends in a second direction perpendicular to the first direction continuously from the other end of the opposite ends of the third section.

A semiconductor die and a transmission line structure has a first doped semiconductor substrate and a radio frequency transmission line disposed above the first doped semiconductor substrate. A second doped semiconductor segment is defined in the first doped semiconductor substrate and is arranged in a transverse relationship to a transmission line axis, with a depletion region being defined in areas of the first doped semiconductor substrate adjacent thereto that reduces power loss in signals through the transmission line.

Stacked superconducting integrated circuits with three dimensional resonant clock networks are described. An apparatus, including a first superconducting integrated circuit having a first clock distribution network for distributing a first clock signal in the first superconducting integrated circuit, is provided. The apparatus further includes a second superconducting integrated circuit, stacked on top of the first superconducting integrated circuit, having a second clock distribution network for distributing a second clock signal in the second superconducting integrated circuit, where each of the first clock distribution network and the second clock distribution network comprises a clock structure having a plurality of unit cells, where each of the plurality of unit cells includes at least one spine and at least one stub, the at least one stub inductively coupled to a first superconducting circuit, and where each of the first clock signal and the second clock signal has a same resonant frequency.

An antenna in package (AIP) 400 includes an IC die 120 including bond pads 121 and a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layer 418 including a top dielectric layer 418b, a top metal layer 418a including an antenna 418a1, and a bottom layer 415 including a bottom dielectric 415b and a bottom metal layer 415a including contact pads including a first contact pad 415a1, and filled vias 415c, 417c. The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillar 132a are electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.