Patent classifications
H01S5/0208
Electrical isolation in photonic integrated circuits
A method of providing electrical isolation between subsections in a waveguide structure for a photonic integrated device, the structure comprising a substrate, a buffer layer and a core layer, the buffer layer being located between the substrate and the core and comprising a dopant of a first type, the first type being either n-type or p- type, the method comprising the steps of prior to adding any layer to a side of the core layer opposite to the buffer layer: selecting at least one area to be an electrical isolation region, applying a dielectric mask to a surface of the core layer opposite to the buffer layer, with a window in the mask exposing an area of the surface corresponding to the selected electrical isolation region, implementing diffusion of a dopant of a second type, the second type being of opposite polarity to the first type, and allowing the dopant of the second type to penetrate to the substrate to form a blocking junction.
Method for fabricating an elctro-absorption modulated laser and electro-absorption modulated laser
It is provided a method for fabricating an electroabsorption modulated laser comprising generating a single mode laser section and an electroabsorption modulator section, comprising fabricating at least one n-doped layer of the laser section and at least one n-doped layer of the modulator section; generating an isolating section for electrically isolating at least the n-doped layer of the laser section and the n-doped layer of the modulator section from one another. Generating the isolating section comprises epitaxially growing at least one isolating layer and structuring the isolating layer before the generation of the n-doped layer of the laser section and the n-doped layer of the modulator section.
Method for producing a light source and light source
A light source comprises a GeSn active zone inserted between two contact zones. The active zone is formed directly on a silicon oxide layer by a first lateral epitaxial growth of a Ge germination layer followed by a second lateral epitaxial growth of a GeSn base layer. A cavity is formed between the contact zones by encapsulation and etching, so as to guide these lateral growths. A vertical growth of GeSn is then achieved from the base layer to form a structural layer. The active zone is formed in the stack of base and structural layers.
SEMICONDUCTOR OPTICAL INTEGRATED DEVICE
A semiconductor optical integrated device comprises a semiconductor amplifier and a plurality of semiconductor lasers, wherein the semiconductor amplifier and the semiconductor lasers are monolithically integrated on a semiconductor substrate, an n-side cladding layer of the semiconductor amplifier and an n-side cladding layer of each of the semiconductor lasers are electrically insulated by an insulating layer formed between the semiconductor substrate and the n-side cladding layer of the semiconductor lasers and an insulating layer formed between the n-side cladding layer of the semiconductor amplifier and the n-side cladding layer of the semiconductor lasers, the n-side cladding layer of the semiconductor lasers and the p-side cladding layer of the semiconductor amplifier is configured to be electrically connected, and the semiconductor amplifier and each semiconductor laser of the plurality of semiconductor lasers are electrically connected in series.
Temperature sensor integrated with MOS capacitor for stabilizing lasers
Techniques and circuitry for a semiconductor laser with enhanced lasing wavelengths stabilization are described. A semiconductor laser can generate an optical signal (e.g., single or multi-wavelength), for use in a Dense Wavelength Division Multiplexing (DWDM) interconnect system. The stabilization circuitry can include temperature sensor circuitry that measures an operational temperature of the semiconductor laser, and a feedback controller that can determine a temperature-induced wavelength shift that may be experienced by the multi-wavelength optical signal based on the laser's temperature. The feedback controller is also configured to generate a compensation signal that is determined to cause a complimentary shift in the multi-wavelength optical signal, where the complimentary shift can compensate for the temperature-induced wavelength shift. An integrated MOS capacitor of the laser can be charged by the signal in a manner that effectuates the complimentary shift and tunes the multi-wavelength optical signal to compensate for temperature-induced shift, thereby enhancing stabilization.
Tunable multilayer terahertz magnon generator
A method for tuning the frequency of THz radiation is provided. The method utilizes an apparatus comprising a spin injector, a tunnel junction coupled to the spin injector, and a ferromagnetic material coupled to the tunnel junction. The ferromagnetic material comprises a Magnon Gain Medium (MGM). The method comprises the step of applying a bias voltage to shift a Fermi level of the spin injector with respect to the Fermi level of the ferromagnetic material to initiate generation of non-equilibrium magnons by injecting minority electrons into the Magnon Gain Medium. The method further comprises the step of tuning a frequency of the generated THz radiation by changing the value of the bias voltage.
DENSE WAVELENGTH DIVISION MULTIPLEXING (DWDM) PHOTONIC INTEGRATION PLATFORM
A Dense Wavelength Division Multiplexing (DWDM) photonic integration circuit (PIC) that implements a DWDM system, such as a transceiver, is described. The DWDM PIC architecture includes photonic devices fully integrating on a single manufacturing platform. The DWDM PIC has a multi-wavelength optical laser, a quantum dot (QD) laser with integrated heterogeneous metal oxide semiconductor (H-MOS) capacitor, integrated on-chip. The multi-wavelength optical laser can be a symmetric comb laser that generates two equal outputs of multi-wavelength light. Alternatively, the DWDM PIC can be designed to interface with a stand-alone multi-wavelength optical laser that is off-chip. In some implementations, the DWDM PIC integrates multiple optimally designed photonic devices, such as a silicon geranium (SiGe) avalanche photodetector (APD), an athermal H-MOS wavelength splitter, a QD photodetector, and a heterogenous grating coupler. Accordingly, fabricating the DWDM PIC includes a unique III-V to silicon bonding process, which is adapted for its use of SiGe APDs.
Pixel array implemented on photonic integrated circuit (PIC)
An optoelectronic device includes a substrate and at least three emitters, which are disposed on the substrate and are configured to emit respective beams of light. A plurality of waveguides are disposed on the substrate and have respective input ends coupled to receive the beams of light from respective ones of the emitters, and curve adiabatically from the input ends to respective output ends of the waveguides, which are arranged on the substrate in an array having a predefined pitch. Control circuitry is configured to apply a temporal modulation independently to each of the beams of light.
ELECTRICALLY ISOLATING VERTICAL-EMITTING DEVICES
A device includes a substrate, a vertical cavity surface emitting laser (VCSEL) array on top of the substrate, a via through the substrate and the VCSEL array, a first electrode extended from a top of the VCSEL array to a bottom of the substrate, through the via, the first electrode electrically connected to the VCSEL array, a second electrode on the bottom of the substrate, the second electrode electrically connected to the VCSEL array, and an isolator in the via providing electrical isolation between the first electrode and the second electrode.
Semiconductor laser device and method for manufacturing the same
A mesa (34) includes a resonator and a second conductivity type contact layer (24). Grooves (32) are provided on both sides of the mesa (34). The first conductivity type contact layer (12) and a side face of the mesa (34) including an end face of the resonator construct an L shape (50). The first conductivity type contact layer (12) constructs bottom surfaces of the L shape (50) and the grooves (32). A side face of the groove (32) includes a slope (38) near the bottom surface (46) and a side face (42) above. A side face of the L shape (50) includes a slope (40) near the bottom surface (48) and a side face (44) above. A first electrode (28) is connected to the first conductivity type contact layer (12) at the bottom surface (46) of the groove (32). A second electrode (30) is connected to the second conductivity type contact layer (24) above the mesa (34).