Patent classifications
H01S5/0218
Coherent single photon source
The invention relates to coherent single photon sources that provide photons with a high degree of indistinguishability. It is a disadvantage of single photon sources based on QDs in nanophotonic structures that, even at low temperatures, acoustic vibrations interact with the QDs to reduce the coherence of the emitted spectrum. The invention uses mechanical clamping of the nanostructure to damp vibrations leading to a weaker QD—phonon coupling and a higher degree of indistinguishability between successively emitted photons. The clamp is mechanically connected to the length of the photonic nanostructure and has a stiffness and a size sufficient to suppress low frequency vibrations (ω≤10 GHz) in a combined structure of the clamp and the nanostructure.
Fabrication of semiconductor structure having group III-V device on group IV substrate with separately formed contacts using different metal liners
In fabricating a semiconductor structure, a group IV substrate and a group III-V chiplet are provided. The group III-V chiplet is bonded to the group IV substrate, and patterned to produce a patterned group III-V device. A blanket dielectric layer is formed over the patterned group III-V device. A first contact hole is formed in the blanket dielectric layer over a first portion of the patterned group III-V device. A first liner stack and a first filler metal are subsequently formed in the first contact hole. A second contact hole is formed in the blanket dielectric layer over a second portion of the patterned group III-V device. A second liner stack and a second filler metal are subsequently formed in the second contact hole. A first bottom metal liner of the first liner stack can be different from a second bottom metal liner of the second liner stack.
III-V LASER PLATFORMS ON SILICON WITH THROUGH SILICON VIAS BY WAFER SCALE BONDING
A laser integrated photonic platform to allow for independent fabrication and development of laser systems in silicon photonics. The photonic platform includes a silicon substrate with an upper surface, one or more through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate. The photonic platform includes a silicon substrate wafer with through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate for mating the photonic platform to a photonics integrated circuit. The photonic platform also includes a III-V semiconductor material structure wafer, where the III-V wafer is bonded to the upper surface of the silicon substrate and includes at least one active layer forming a light source for the photonic platform.
SIDE MODE SUPPRESSION FOR EXTENDED C-BAND TUNABLE LASER
A method for improving wide-band wavelength-tunable laser. The method includes configuring a gain region between a first facet and a second facet and crosswise a PN-junction with an active layer between P-type cladding layer and N-type cladding layer. The method further includes coupling a light excited in the active layer and partially reflected from the second facet to pass through the first facet to a wavelength tuner configured to generate a joint interference spectrum with multiple modes separated by a joint-free-spectral-range (JFSR). Additionally, the method includes configuring the second facet to have reduced reflectivity for increasing wavelengths. Furthermore, the method includes reconfiguring the gain chip with an absorption layer near the active layer to induce a gain loss for wavelengths shorter than a longest wavelength associated with a short-wavelength side mode. Moreover, the method includes outputting amplified light at a basic mode via the second facet.
SEMICONDUCTOR DEVICE AND FABRICATION METHOD
A semiconductor device comprising a nominally or exactly or equivalent orientation silicon substrate on which is grown directly a <100 nm thick nucleation layer (NL) of a III-V compound semiconductor, other than GaP, followed by a buffer layer of the same compound, formed directly on the NL, optionally followed by further III-V semiconductor layers, followed by at least one layer containing III-V compound semiconductor quantum dots, optionally followed by further III-V semiconductor layers. The NL reduces the formation and propagation of defects from the interface with the silicon, and the resilience of quantum dot structures to dislocations enables lasers and other semiconductor devices of improved performance to be realized by direct epitaxy on nominally or exactly or equivalent orientation silicon.
MANUFACTURABLE MULTI-EMITTER LASER DIODE
A multi-emitter laser diode device includes a carrier chip singulated from a carrier wafer. The carrier chip has a length and a width, and the width defines a first pitch. The device also includes a plurality of epitaxial mesa dice regions transferred to the carrier chip from a substrate and attached to the carrier chip at a bond region. Each of the epitaxial mesa dice regions is arranged on the carrier chip in a substantially parallel configuration and positioned at a second pitch defining the distance between adjacent epitaxial mesa dice regions. Each of the plurality of epitaxial mesa dice regions includes epitaxial material, which includes an n-type cladding region, an active region having at least one active layer region, and a p-type cladding region. The device also includes one or more laser diode stripe regions, each of which has a pair of facets forming a cavity region.
FABRICATION OF SEMICONDUCTOR STRUCTURES
The invention relates to a method for fabricating a semiconductor structure. The method comprises fabricating a photonic crystal structure of a first material, in particular a first semiconductor material and selectively removing the first material within a predefined part of the photonic crystal structure. The method further comprises replacing the first material within the predefined part of the photonic crystal structure with one or more second materials by selective epitaxy. The one or more second materials may be in particular semiconductor materials. The invention further relates to devices obtainable by such a method.
SEMICONDUCTOR OPTICAL DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR OPTICAL DEVICE
A method for producing a semiconductor optical device includes the steps of bonding a semiconductor chip to an SOI substrate having a waveguide, the semiconductor chip having an optical gain and including a first cladding layer, a core layer, and a second cladding layer that contain III-V group compound semiconductors and are sequentially stacked in this order, forming a covered portion with a first insulating layer on the second cladding layer, etching partway in the thickness direction the second cladding layer exposed from the first insulating film, forming a second insulating film covering from the covered portion to a part of a remaining portion of the second cladding layer, and forming a first tapered portion that is disposed on the waveguide and tapered along the extending direction of the waveguide by etching the core layer and the second cladding layer exposed from the second insulating film.
METHODS OF MANUFACTURE OF ADVANCED WAFER BONDED HETEROJUNCTION BIPOLAR TRANSISTORS
Methods of manufacturing heterojunction bipolar transistors are described herein. An exemplary method can include providing an emitter/base stack comprising a substrate, a base over the substrate, and/or an emitter over the base. The exemplary method further can include forming a collector. The exemplary method also can include wafer bonding the base to the collector. Other embodiments are also disclosed herein.
Intermediate ultraviolet laser diode device
An intermediate ultraviolet laser diode device includes a gallium and nitrogen containing substrate member comprising a surface region, a release material overlying the surface region, an n-type gallium and nitrogen containing material; an active region overlying the n-type gallium and nitrogen containing material; a p-type gallium and nitrogen containing material; a first transparent conductive oxide material overlying the p-type gallium and nitrogen containing material; and an interface region overlying the first transparent conductive oxide material.