Methods for forming an at least partially oxidized confinement layer of a semiconductor device and corresponding semiconductor devices are provided. The method comprises forming two or more layers of a semiconductor device on a substrate. The layers include an exposed layer and a to-be-oxidized layer. The to-be-oxidized layer is disposed between the substrate and the exposed layer. The method further comprises etching, using a masking process, a pattern of holes that extend through the exposed layer at least to a first surface of the to-be-oxidized layer. Each hole of the pattern of holes extends in a direction that is transverse to a level plane that is parallel to the first surface of the to-be-oxidized layer. The method further comprises oxidizing the to-be-oxidized layer through the pattern of holes by exposing the two or more layers of the semiconductor device to an oxidizing gas to form a confinement layer.

An array layout of VCSELs is intentionally mis-aligned with respect to the xy-plane of the device structure as defined by the crystallographic axes of the semiconductor material. The mis-alignment may take the form of skewing the emitter array with respect to the xy-plane, or rotating the emitter array. In either case, the layout pattern retains the desired, row/column structure (necessary for dicing the structure into one-dimensional arrays) while reducing the probability that an extended defect along a crystallographic plane will impact a large number of individual emitters.

Modification of the topology of selected regions of individual VCSEL devices during fabrication is utilized to provide an array output beam with specific characteristics (e.g., “uniform” output power across the array). These physical features include the width of the metal aperture, the width of the modal filter, and/or the geometry of the contact ring structure on the top of the VCSEL device. The modifications may also function to adjust the numerical apertures (NAs) of the devices, the beam waist, wallplug efficiency, and the like.

A beam deflection device includes multiple light-emission structures arranged adjacent to each other in a first direction (X direction). The light-emission structures are each configured to be capable of emitting, from its device surface, a line beam that extends in the first direction in the far field. Furthermore, the light-emission structures are each configured to allow the line beam to be scanned in a second direction (Y direction) that is orthogonal to the first direction.

A light emitting element includes a laminated structure 20 in which a first compound semiconductor layer 21, an active layer 23, and a second compound semiconductor layer 22 are laminated, a first light reflecting layer 41, and a second light reflecting layer 42 having a flat shape, a base surface 90 located on a side of a first surface of the first compound semiconductor layer 21 has a first region 91 (upwardly convex first-A region 91A and first-B region 91B) including a protruding portion protruding in a direction away from the active layer and a second region 92 having a flat surface, the first light reflecting layer 41 is formed at least on the first-A region 91A, a second curve formed by the first-B region 91B and a straight line formed by the second region 92 intersects at an angle exceeding 0°, and the second curve includes at least one kind of figure selected from the group consisting of a combination of a downwardly convex curve, a line segment, and an arbitrary curve.

A semiconductor surface-emitting laser array can be provided with a group of independently addressable light-emitting pixels arranged in at least two rows and in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each pixel. An aggregate linear pitch can be achieved between pixels of the at least two rows along the linear array in a cross process direction that is less than the size of a pixel. The semiconductor laser array can include more than one common substrate chip tiled and stitched together in a staggered arrangement to provide an at least 11-inch wide, 1200pdi imager with timing delays associated with each of the more than one common substrate chip in the staggered arrangement.

A 3D package for semiconductor thermal management can include a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough, a first tubular connection for providing cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel. Integrated slots can be provided for accepting and mounting semiconductor components. Mounting holes can be formed in the mechanical block for securing optical elements. At least one semiconductor laser array die can be secured to the mechanical block at the integrated slots, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel.

A laser imager for a printing system, comprising a plurality of independently addressable surface emitting lasers arranged in a linear array on a common substrate chip and including a common cathode and a dedicated control channel associated with an address trace line for each laser of the plurality of independently addressable surface emitting lasers, and optical elements arranged in a linear lens array configured to capture and focus light from the plurality of independently addressable surface emitting lasers onto a imaging member, wherein the plurality of independently addressable surface emitting lasers arranged in a linear array and the optical elements arranged in a linear lens array operate together to image the imaging member.

A computer adapted to convert images into raw data can provide the raw data to a control interface adapted to transmit the raw data with timing information to an electronic driver circuit. The electronic driver circuit can convert the raw data with the timing information provided by a control interface into regulated current signals provided to the semiconductor laser array at 300 dpi and higher. The semiconductor array can convert the current signals into light to illuminate an imaging member. The laser array can comprise vertical cavity surface emitting lasers providing imaging greater than 300 dpi. Each semiconductor laser can operate at 50 mW or greater.

A method of transferring a semiconductor epi layer onto a metal host substrate is described. An epi layer of a semiconductor chip (e.g., semiconductor laser array) including a substrate can be mounted onto a planar handle wafer with an adhesive, wherein a backside of the substrate faces upward and away from the epi layer and the planar handle wafer. The backside of the substrate can be treated to substantially remove the substrate, while leaving the epi layer undamaged (e.g., by polishing to where no more than 20 micrometers of the substrate remains). Metal can be formed on the treated backside resulting in a metalized backside. The planar handle wafer can then be removed from the epi layer by dissolving the adhesive with a solvent, wherein a modified semiconductor chip remains. The semiconductor chip can be annealed to form a backside ohmic contact interface. The semiconductor chip can then be attached to a mechanical block by the ohmic contact interface.