An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad. The gate pull transistor may be configured to provide a low impedance path between the gate of the driver transistor and the I/O pad or the first rail when an overvoltage signal applied to the I/O pad has a magnitude that exceeds the nominal operating range of voltage levels defined for the I/O pad.

An electrostatic protection circuit connected with an internal circuit is provided. The electrostatic protection circuit includes: a first circuit, a first diode connected in parallel with the first circuit, a second circuit, and a second diode connected in parallel with the second circuit. The first circuit is connected between a power supply pad and an internal circuit input terminal. The second circuit is connected between the internal circuit input terminal and a ground pad. The first circuit and the second circuit are diode-triggered silicon controlled rectifier circuits. The technical solution of the disclosure can improve electrostatic protection capability of a charged device model of a chip.

An ESD clamp circuit has an ESD detection circuit connected between a first terminal and a second terminal, with a first output node and a second output node. The ESD detection circuit is configured to output respective first and second control signals at the first and second output nodes in response to an ESD event. A discharge circuit includes a p-type transistor having a source, a drain and a gate, with the gate connected to the first output node. An n-type transistor has a source, a drain and a gate, with the gate connected to the second output node. The drain is connected to the drain of the p-type transistor. The discharge circuit is configured to establish a first ESD discharge path from the first terminal, through the p-type transistor and the n-type transistor, to the second terminal, and to further establish a second ESD discharge path in parallel with the first ESD discharge path. The second ESD discharge path includes a parasitic silicon controlled rectifier (SCR).

The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

The present disclosure provides an electrostatic discharge (ESD) protection network for a chip. The chip includes a first power supply pad, a second power supply pad, and a ground pad. The ESD protection network includes: a first ESD protection circuit, located between the first power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the first power supply pad; a second ESD protection circuit, located between the second power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the second power supply pad; and a third ESD protection circuit, configured to provide a discharge path for an electrostatic charge between the first power supply pad and the second power supply pad.

The present disclosure provides an electrostatic discharge (ESD) protection circuit and a chip. The ESD protection circuit is connected between a power supply VDD and a ground VSS, and includes a filter branch, a first inverter group, a switch transistor, a clamp transistor, a feedback transistor, and a second inverter group. The first inverter group has two terminals respectively connected to a first node and a second node. The switch transistor has a gate connected to the second node. The clamp transistor has a gate connected to a fourth node. The feedback transistor has a gate connected to the fourth node. The second inverter group has two terminals respectively connected to a third node and the fourth node.

An electro-static discharge (ESD) protection network for an input/output (I/O) pad includes a driver stack including an upper branch and a lower branch, the upper branch being electrically connected between a first node that has a first reference voltage and the I/O pad, and the lower branch being electrically connected between the I/O pad and a second node that has a second reference voltage; a first ESD device electrically connected between the I/O pad and a third node that has a third reference voltage; and a power clamp between the third node and the second node.

An electrostatic discharge protection circuit includes a pull-down switch, a dummy pattern arranged parallel to the pull-down switch in a first direction, clamp switches arranged parallel to each other in the first direction between the dummy pattern and the pull-down switch, and a resistor configured to transfer a power supply voltage supplied through a power terminal to a gate pattern of the pull-down switch by being arranged parallel to the pull-down switch. Drains of the clamp switches are coupled in common to the power terminal, sources of the clamp switches are coupled in common to a ground terminal, and a first end of the pull-down switch and a second end of the resistor are coupled to each other through a first conductive line extending in the first direction, the pull-down switch, the resistor and the first conductive line are formed in a same layer.

To provide a semiconductor device with a tolerant buffer capable of protecting the internal circuit even when the power supply potential is turned 0 [V]. In the semiconductor device, the protection voltage generating circuit 100 generates the larger of the divided voltage and the power supply voltage Vdd obtained by dividing the voltage padv applied to the pad 4 as the protection voltage protectv. The first protection circuit 200 for protecting the internal logic circuit 2A,2B and the output buffer 10 and the second protection circuit 300 for protecting the input buffer 20 operate protectv this protection voltage.

An apparatus includes a first diode and a second diode connected in series between a first voltage terminal and a second voltage terminal, a switch connected between the first voltage terminal and the second voltage terminal, and a clamping threshold circuit connected between a common node of the first diode and the second diode, and a gate of the switch, wherein the clamping threshold circuit is configured such that in response to a voltage surge applied to the common node of the first diode and the second diode, the switch is turned on once the voltage surge is greater than a predetermined threshold.