A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.

A charging port protection apparatus and a terminal related to the field of terminal technologies are provided, including a first detection circuit, a first discharge circuit, a second detection voltage, and a switch circuit. The first detection circuit generates a first detection voltage based on a peak voltage of an input voltage. The first discharge circuit discharges the peak voltage based on the first detection voltage. The second detection circuit generates a second detection voltage when the input voltage is greater than a first threshold. The switch circuit disconnects the input voltage based on the second detection voltage. This implements not only protection against an ESD and EOS peak voltage, but also protection against a high-voltage direct current. The protection against the peak voltage and the protection against the high-voltage direct current are not mutually limited, which implements protection against impact of electrical over-stress in various forms.

The present disclosure provides an electro-static discharge protection device for a semiconductor, including: a substrate of a first conductive type, a deep well region of a second conductive type being formed in the substrate of the first conductive type; first diodes, located in the deep well region of the second conductive type, anodes of the first diodes being connected to a first voltage through a plurality of first metal lines; second diodes, located in the deep well region of the second conductive type; a first pad, connected to the anodes of the first diodes through the plurality of first metal lines, and connected to the first voltage; a second pad, connected to cathodes of the second diodes through a plurality of second metal lines, and connected to a second voltage.

An electrical wiring device including a ground fault interrupt assembly, the ground fault interrupt assembly comprising a ground fault interrupt circuit, being formed on a first printed circuit board, and a trip mechanism, the ground fault interrupt circuit being configured to detect a differential current between the line conductor and the neutral conductor and to trigger the trip mechanism to electrically decouple the plurality of line terminals from the plurality of load terminals, according to a predetermined criterion, based, at least in part, on the different current; and a USB power supply circuit being formed on a second printed circuit board disposed within the compartment, the USB power supply circuit providing to the at least one USB port, wherein the first printed circuit board and the second printed circuit board are separated by a distance within the inner compartment.

A device includes a diode circuit. The diode circuit is coupled between a first input/output (I/O) pin and a second I/O pin of a circuit, and is configured to be turned off. The diode circuit is configured to provide a first discharging path for the first I/O pin of the circuit and a second discharging path for the second I/O pin of the circuit. The diode circuit includes a first transistor and a second transistor. The first transistor is between a node and the first I/O pin. The second transistor is between the node and the second I/O pin. The node is configured to receive a first voltage, and control terminals of the first transistor and the second transistor are configured to receive a second voltage. A voltage difference between the first voltage and the second voltage is configured to turn off the first transistor and the second transistor.

The present disclosure relates to a transient voltage suppression device comprising a single crystal semiconductor substrate doped with a first conductivity type comprising first and second opposing surfaces, a semiconductor region doped with a second conductivity type opposite to the first conductivity type extending into the substrate from the first surface, a first electrically conductive electrode on the first side contacting the semiconductor region and a second electrically conductive electrode on the second side contacting the substrate, a first interface between the substrate and the semiconductor region forming the junction of a TVS diode and a second interface between the first electrically conductive electrode and the semiconductor region or between the substrate and the second electrically conductive electrode forming the junction of a Schottky diode.

An electrostatic discharge (ESD) circuit is used to protect an internal circuit. The ESD circuit includes: an ESD clamp, having a first terminal connected to a power and a second terminal connected to a ground voltage; and a first switch, connected between an ESD terminal of the ESD clamp and the internal circuit. A gate of the first switch is controlled by a state signal in the ESD clamp to turn off the first switch when an ESD event occurs on the first terminal of the ESD clamp and turn on the first switch when the ESD event does not occur.

A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.

An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a primary ESD protection unit electrically connected to a first node and to a second node and configured to shunt current in response to an ESD pulse received between the first and second nodes and a secondary ESD protection unit electrically connected to the primary ESD protection unit and to the second node and configured to shunt current in response to the ESD pulse to keep an output voltage of the ESD protection device to be within a safe operating voltage range of a device to be protected. Other embodiments are also described.