An interlocking adapter in one aspect of the present disclosure includes a current path, an electric load, a switch, and a controller. The controller turns on and off the switch in synchronization with a change of an alternating-current voltage received from an electric outlet of an electric apparatus in response to reception of an interlocking command signal from a working machine so as to supply a load current from the electric outlet to the electric load. The controller turns on and off the switch at a specified ratio of a time every cycle of the alternating-current voltage.

A command device is connected with a serial line to a driving device for controlling operations of a plurality of first switching elements and one or more second switching elements. The command device includes a command signal generator to generate a plurality of first command signals and one or more second command signals, an encoder to generate encoded data by encoding at least some signals of the plurality of first command signals and the one or more second command signals, and a command-device serializer to generate serial command data through serial conversion of the encoded data and transmit the serial command data to the driving device via the serial line.

A load control device for controlling the amount of power delivered from an AC power source to an electrical load is operable to conduct enough current through a thyristor of a connected dimmer switch to exceed rated latching and holding currents of the thyristor. The load control device comprises a controllable-load circuit operable to conduct a controllable-load current through the thyristor of the dimmer switch. The load control device disables the controllable-load circuit when the phase-control voltage received from the dimmer switch is a reverse phase-control waveform. When the phase-control voltage received from the dimmer switch is a forward phase-control waveform, the load control device is operable to decrease the magnitude of the controllable-load current so as to conduct only enough current as is required in order to exceed rated latching and holding currents of the thyristor.

A computer system comprising a processor device configured to switch between switching modes of a load is presented. The switching modes are a complementary switching mode and a non-complementary switching mode of an upper switch and a lower switch of a first half-bridge converter configured to provide a wanted power to a load. The processor device is configured to provide a first upper control signal to the upper switch and a first lower control signal to the lower switch as center aligned PWM-signals at a first PWM period. Responsive to determining that a current switching mode is to be changed at a second PWM period, the processor device is further configured to determine a time-shift for shifting the first upper control signal and the first lower control signal, and to provide the first upper control signal shifted by the time-shift to the upper switch and the first lower control signal shifted by the time-shift to the lower switch at the second PWM period.

A multiphase inverter circuit and a modulation method thereof. The multiphase inverter circuit is configured for generating a target alternating current power based on a direct current power provided by a DC power supply, and the multiphase inverter circuit includes at least one non-interleaved inverter circuit; the non-interleaved inverter circuit includes: a first bridge arm unit, a second bridge arm unit, and an inverting coupling transformer. When the first pulse signal and the second pulse signal with a phase difference pass through the inverting coupling transformer, a current loop can be formed within the non-interleaved inverter circuit so that the body diodes of the power transistors conduct before the power transistors conduct, thereby reducing the reverse recovery power consumption of the body diode of the corresponding power transistor and realizing zero-voltage soft switching.

A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference V.sub.ref in an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.

An electronic pre-charge relay device according to an embodiment of the present invention comprises: a control signal input unit for inputting a control signal for turning on and off; an AC conversion unit for converting the control signal into an AC signal; an insulating transform unit for boosting the converted AC control signal to a predetermined voltage level; a rectifying and smoothing unit for converting the boosted AC control signal into a DC input signal; a power semiconductor switch having a gate used to turn on and off to supply electrical energy to a load in relation to the control signal; and a gate signal generation unit for generating at least one gate signal suitable for the power semiconductor switch by using the converted DC input signal.

The present provides a sensing circuit, a set of pre-amplifiers, and an operating method thereof. The set of pre-amplifiers includes a first pre-amplifier and a second pre-amplifier. The first pre-amplifier is coupled to a first input terminal of the sense amplifier. The second pre-amplifier is coupled to a second input terminal of the sense amplifier. The first pre-amplifier and the second pre-amplifier respectively performs a discharging operation to discharge the first input terminal and the second input terminal of the sense amplifier after the first input terminal and the second input terminal of the sense amplifier are charged to a predetermined voltage. One of the first pre-amplifier and the second pre-amplifier amplifies a voltage difference between the first input terminal and the second input terminal of the sense amplifier by terminating the discharging operation of another of the first pre-amplifier and the second pre-amplifier.

A load control device for controlling the amount of power delivered from an AC power source to an electrical load is operable to conduct enough current through a thyristor of a connected dimmer switch to exceed rated latching and holding currents of the thyristor. The load control device comprises a controllable-load circuit operable to conduct a controllable-load current through the thyristor of the dimmer switch. The load control device disables the controllable-load circuit when the phase-control voltage received from the dimmer switch is a reverse phase-control waveform. When the phase-control voltage received from the dimmer switch is a forward phase-control waveform, the load control device is operable to decrease the magnitude of the controllable-load current so as to conduct only enough current as is required in order to exceed rated latching and holding currents of the thyristor.

A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference V.sub.ref in an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.