A method of controlling a power converter in a power transmission network. A first amplitude limit value for a first AC current output from an AC side of the power converter is received. A second amplitude limit value for a negative phase sequence component of the first AC current is received. The negative phase sequence component is measured to provide a measured second amplitude. The negative phase sequence component is regulated to flow with a second amplitude that is the lesser of the measured second amplitude and second amplitude limit value. A positive phase sequence component of the first AC current is regulated to flow with an amplitude not exceeding a regulated third amplitude. The third amplitude is set using a function such that the second amplitude and the third amplitude provide a first amplitude for the first AC current that is substantially equal to the first amplitude limit value.

A multi-phase controller includes a summer circuit configured to sense a plurality of phase currents generated by a plurality of power stages and generate a summed current value representative of a total current generated by the plurality of power stages; and a current limit controller configurable in a current-limit mode or a non-current-limit mode based on the summed current value and configured to limit the total current to a predefined value during the current-limit mode. The current limit controller includes a threshold selector circuit and a mode configuration circuit. The threshold selector circuit selects a first threshold or a second threshold as a selected threshold based on a configuration signal. The mode configuration circuit monitors a duration during which a comparison result indicates that the summed current value satisfies the selected threshold, and generates the configuration signal based on whether the first duration satisfies a duration threshold.

An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

A gate driving circuit for an insulated gate-type power semiconductor element includes an Nch MOSFET which turns on the insulated gate-type power semiconductor element, a Pch MOSFET which turns off the insulated gate-type power semiconductor element, a control circuit which turns on the Nch MOSFET by applying a positive voltage to the gate electrode of the Nch MOSFET, and which turns on the Pch MOSFET by applying a negative voltage to the gate electrode of the Pch MOSFET, and a power supply which applies a negative voltage to the drain electrode of the Pch MOSFET and to a negative-side electrode of the control circuit, which applies a positive voltage to the drain electrode of the Nch MOSFET, and which applies to a positive-side electrode of the control circuit a positive voltage whose absolute value is larger than absolute value of the positive voltage applied to the drain electrode of the Nch MOSFET.

A controller for controlling a power stage having one or more phases is presented. The controller includes a reference circuit that generates a reference signal; a ramp generator generating a feedback ramp signal based on a feedback signal of the power stage; and a modulator generating a control signal for controlling at least one phase of the power stage. The control signal may include a series of pulses in which each pulse is associated with a corresponding phase of the power stage.

A load control device for controlling the amount of power delivered from an AC power source to an electrical load is operable to conduct enough current through a thyristor of a connected dimmer switch to exceed rated latching and holding currents of the thyristor. The load control device comprises a controllable-load circuit operable to conduct a controllable-load current through the thyristor of the dimmer switch. The load control device disables the controllable-load circuit when the phase-control voltage received from the dimmer switch is a reverse phase-control waveform. When the phase-control voltage received from the dimmer switch is a forward phase-control waveform, the load control device is operable to decrease the magnitude of the controllable-load current so as to conduct only enough current as is required in order to exceed rated latching and holding currents of the thyristor.

A variable de-energizing phase duty cycle D.sub.d is generated based on an input signal to optimize for a low duty cycle in a freewheeling phase. A variable energizing phase duty cycle D.sub.e is generated based on a buck-boost control loop tracking the input signal. A tri-state buck-boost converter is controlled using the variable energizing phase duty cycle D.sub.e and the variable de-energizing phase duty cycle D.sub.d.

A load control device for controlling the amount of power delivered from an AC power source to an electrical load is operable to conduct enough current through a thyristor of a connected dimmer switch to exceed rated latching and holding currents of the thyristor. The load control device comprises a controllable-load circuit operable to conduct a controllable-load current through the thyristor of the dimmer switch. The load control device disables the controllable-load circuit when the phase-control voltage received from the dimmer switch is a reverse phase-control waveform. When the phase-control voltage received from the dimmer switch is a forward phase-control waveform, the load control device is operable to decrease the magnitude of the controllable-load current so as to conduct only enough current as is required in order to exceed rated latching and holding currents of the thyristor.

In one embodiment, a multi-level, bridgeless boost power factor correction (PFC) device, comprising: a circuit comprising an inductor, and at least a first pair and a second pair of switches and a capacitor arranged in a flying capacitor, totem-pole configuration; and a control circuit configured to drive the at least first and second pairs of switches in such a way as to reduce distortion in a line current, wherein for the first and second pairs of switches, the control circuit is configured to: for a first half line cycle, drive a first switch of each pair during an entire interval of the first half-line cycle and a second switch of each pair for less than the entire interval; and for a second half-line cycle, drive the first switch of each pair for less than an entire interval of the second half-line cycle and the second switch of each pair during an entire interval of the second half-line cycle.

A multi-phase controller includes a summer circuit configured to sense a plurality of phase currents generated by a plurality of power stages and generate a summed current value representative of a total current generated by the plurality of power stages; and a current limit controller configurable in a current-limit mode or a non-current-limit mode based on the summed current value and configured to limit the total current to a predefined value during the current-limit mode. The current limit controller includes a threshold selector circuit and a mode configuration circuit. The threshold selector circuit selects a first threshold or a second threshold as a selected threshold based on a configuration signal. The mode configuration circuit monitors a duration during which a comparison result indicates that the summed current value satisfies the selected threshold, and generates the configuration signal based on whether the first duration satisfies a duration threshold.