A circuit arrangement has an even number of semiconductor switches, which are connected in series and contain in each case two load terminals and a control terminal and are associated with one another in pairs. The circuit arrangement also contains, for each semiconductor switch, a driver for actuating the semiconductor switch via the control terminal thereof and, for every two semiconductor switches that form a switch pair, contains a switching power supply which is supplied with energy from an electrical voltage between the two load terminals of a first semiconductor switch of the switch pair and supplies both the driver of the first semiconductor switch and the driver of the second semiconductor switch of the switch pair with energy.

A circuit arrangement has an even number of semiconductor switches, which are connected in series and contain in each case two load terminals and a control terminal and are associated with one another in pairs. The circuit arrangement also contains, for each semiconductor switch, a driver for actuating the semiconductor switch via the control terminal thereof and, for every two semiconductor switches that form a switch pair, contains a switching power supply which is supplied with energy from an electrical voltage between the two load terminals of a first semiconductor switch of the switch pair and supplies both the driver of the first semiconductor switch and the driver of the second semiconductor switch of the switch pair with energy.

To suppress a leakage current flowing through a parasitic capacitor of an insulated transformer of a high-side insulated power. The present invention suppresses a common mode current using a common mode reactor by focusing on the fact that a leakage current flowing through a parasitic capacitor of an insulated transformer of a high-side insulated power source resulting from a high-frequency signal generated due to an on/off operation of a high-side switching element is the common mode current. The common mode reactor reduces the common mode current and bears the high-frequency signal to prevent the high-frequency signal from being applied to the insulated transformer of the high-side insulated power source, suppress the leakage current flowing through the parasitic capacitor of the insulated transformer, and reduce an erroneous operation of the high-side switching element generated due to the leakage current flowing through the parasitic capacitor of the insulated transformer.

To suppress a leakage current flowing through a parasitic capacitor of an insulated transformer of a high-side insulated power. The present invention suppresses a common mode current using a common mode reactor by focusing on the fact that a leakage current flowing through a parasitic capacitor of an insulated transformer of a high-side insulated power source resulting from a high-frequency signal generated due to an on/off operation of a high-side switching element is the common mode current. The common mode reactor reduces the common mode current and bears the high-frequency signal to prevent the high-frequency signal from being applied to the insulated transformer of the high-side insulated power source, suppress the leakage current flowing through the parasitic capacitor of the insulated transformer, and reduce an erroneous operation of the high-side switching element generated due to the leakage current flowing through the parasitic capacitor of the insulated transformer.

An auxiliary power supply circuit is configured to receive electric power from an auxiliary power supply having a positive electrode connected to a switch node and supply electric power to a capacitor having a positive electrode connected to a reference potential node. The auxiliary power supply circuit includes; a switch element connected between the reference potential node and the switch node; and a diode having an anode connected to a negative electrode of the capacitor and a cathode connected to a negative electrode of the auxiliary power supply, a voltage of the switch node being alternately switched between (i) a first voltage substantially equal to a voltage of the reference potential node and (ii) a second voltage higher than the first voltage.

The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal. During a decoding process, a voltage at a charge-discharge capacitor of the capacitor charge-discharge decoding module before the charging and discharging is a common mode voltage VCM, and a voltage at a charge-discharge node after the end of the charging and discharging is a voltage V.sub.C, and the PWM signal is decoded by identify the PWM signal through determining a polarity of a voltage difference between the common mode voltage VCM and the voltage V.sub.C. The present disclosure further provides a method of decoding based on a capacitor charge-discharge structure. The present disclosure provides a simple structure and does not need synchronize code streams, thus avoiding the use of a complicated CDR and an oversampling structure, realizing the decoding of PWM signals at different rates, increasing the efficiency of signal transmission and lowering the power consumption.

The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal. During a decoding process, a voltage at a charge-discharge capacitor of the capacitor charge-discharge decoding module before the charging and discharging is a common mode voltage VCM, and a voltage at a charge-discharge node after the end of the charging and discharging is a voltage V.sub.C, and the PWM signal is decoded by identify the PWM signal through determining a polarity of a voltage difference between the common mode voltage VCM and the voltage V.sub.C. The present disclosure further provides a method of decoding based on a capacitor charge-discharge structure. The present disclosure provides a simple structure and does not need synchronize code streams, thus avoiding the use of a complicated CDR and an oversampling structure, realizing the decoding of PWM signals at different rates, increasing the efficiency of signal transmission and lowering the power consumption.

A modular power supply system, includes: a main controller, configured to output a main control signal; N local controllers, wherein each of the local controllers is configured to receive the main control signal to output at least one local control signal; and N power units, in one-to-one correspondence with the N local controllers, wherein each of the power units includes a first end and a second end, the second end of each of the power units is connected to the first end of an adjacent one of the power units, each of the power units includes M power converters, and each of the power converters is configured to operate according to the local control signal output by a corresponding local controller, wherein each of the power units further includes: M sampling circuits, configured to sample positive DC bus voltages and negative DC bus voltages of the M power converters respectively.

A concentration control circuit can include: a voltage feedback circuit configured to generate a current reference signal representing an error between a voltage reference signal and an output voltage feedback signal shared by each of a plurality of power stage circuits of a multi-phase power converter to adjust a respective phase current; and a clock signal generation circuit configured to generate a clock signal to adjust at least one of switching frequency and phase of each of the power stage circuits, where the clock signal is adjusted in accordance with a change of the current reference signal.

Described is a controller for a DC/DC converter of a type having N power stages, where N is a natural number greater or equal to 2. The controller comprises a decision maker module, a proportional-integral-derivative (PID) or proportional-integral (PI) control module and a transient compression control module. The decision maker module determines a first steady state mode of operation and a second transient mode of operation and is configured to switch control between said first steady state mode of operation to said second transient mode of operation when an operating parameter of one of the N power stages exhibits a predetermined operating condition relative to a predetermined operating limit and/or a predetermined, calculated or selected threshold. The PID or PI module regulates the operating parameter during said first steady state mode of operation. The transient compression control module limits any overshoot, undershoot or imbalances of the operating parameter levels during said second transient mode of operation.