An integrated circuit for a power supply circuit that includes a transformer and a transistor controlling an inductor current flowing through a primary winding of the transformer. The integrated circuit includes a terminal receiving a voltage corresponding to the voltage of a secondary winding of the transformer when the transistor is in an off-state, a first detection circuit detecting that the inductor current is smaller than a first current value, and a determination circuit determining whether an AC voltage applied to the primary winding of the transformer is a first or second AC voltage, both based on the received voltage in the off-state of the transistor. The integrated circuit is configured to drive the transistor in response to a detection result of the first detection circuit, a determination result of the determination circuit, and an output voltage of the power supply circuit generated from the AC voltage.

An Uninterruptible Power Supply (UPS) including an input configured to receive input AC power, a backup power input configured to receive backup DC power having a first voltage level from a backup power source, a converter configured to convert the input AC power from the input and the backup DC power from the backup power input into DC power having a second voltage level, the converter including an input selection circuit configured to selectively couple the converter to the input and the backup power input, an inductor, a first converter switch configured to couple a first end of the inductor to a neutral connection, and a second converter switch configured to couple a second end of the inductor to the backup power input via the input selection circuit.

The present disclosure provides a power factor improvement circuit with a DC/DC converter including an arithmetic circuit. A first voltage having a full-wave rectified waveform is received by an input voltage detection terminal of the power factor improvement circuit. A second voltage is generated by amplifying an error between a first detection voltage and a reference voltage according to an output voltage of the DC/DC converter. A third voltage is generated by multiplying the first voltage by the second voltage. The arithmetic circuit adds an offset voltage to a third voltage to generate a fourth voltage. A comparator is configured to compare a second detection voltage with the fourth voltage. A drive circuit is configured to turn on/off drive of the switching transistor according to an output of the comparator. When the second detection voltage is higher than the fourth voltage, the switching transistor is turned off.

An architecture for a multi-port AC/DC Switching Mode Power Supply (SMPS) with Power Factor Correction (PFC) comprises power management control (PMC) for PFC On/Off Control and Smart Power Distribution, and optionally, a boost follower circuit. For example, in a universal AC/DC multi-port USB-C Power Delivery (PD) adapter, PMC enables turn-on and turn-off of PFC dependent on output port operational status and a combined load of active output ports. A microprocessor control unit (MCU) receives operational status, a voltage sense input and a current sense input for each USB port, computes output power for each USB port, and executes a power distribution protocol to turn-on or turn-off PFC dependent on the combined load from each USB port. Available power may be distributed intelligently to one or more ports, dependent on load. In an example embodiment, turning-off PFC for low load and low AC line input increases efficiency by 3% to 5%.

A control circuit for a power factor correction (PFC) circuit, the control circuit includes a multiplier having first, second, and third multiplier inputs and a multiplier output. The control circuit has an adder having first and second inputs and an output. The first input of the adder is coupled to the multiplier output. The control circuit further includes a root mean square (RMS) calculation circuit configured to determine a square of a root mean square of an input sinusoidal voltage. The RMS calculation circuit has an output coupled to the second multiplier input. An input voltage square calculation circuit is configured to determine a square of the input sinusoidal voltage. The input voltage square calculation circuit has an output coupled to the third multiplier input.

An AC-DC converter includes three phase terminals, first and second DC terminals, a first converter stage for converting between the AC signal and a first signal at first and second intermediate nodes, a second converter stage to convert between a second signal at third and fourth intermediate nodes and the DC signal at the first and second DC terminals. The second converter stage has a first active switch. A link connects the first and third intermediate nodes and the second and fourth intermediate nodes. A current injection circuit has second active switches. In a first mode, the first active switch and the second active switches are operated through PWM. In a second mode, the third and fourth intermediate nodes are continuously connected to the first and second DC terminals such that the second converter stage is inoperative and the second active switches are operated through PWM.

A three-phase AC to DC converter includes a first converter stage for converting between three phase voltages at three phase terminals and a first signal at a first intermediate node and a second intermediate node. A phase selector is configured to selectively connect the three phase terminals to a third intermediate node. The converter includes a second converter stage, a DC link connecting the first and second converter stages, and a galvanically isolated DC/DC converter stage having a first side connected to output nodes of the second converter stage and a first common node. A second side of the DC/DC converter stage is galvanically isolated from the first side. The first common node is connected to the third intermediate node. The difference of a first current applied to the DC/DC converter at output nodes of the second converter stage is provided at the third intermediate node.

Provided are a heat sink capable of suppressing overcooling of an electronic component which should not be overcooled and highly efficiently cooling only an electronic component which should be cooled, and a circuit device including the same. A heat sink includes a pipe and a cooling block. At least one projection is formed in the cooling block. The pipe is in contact with the projection. The pipe is arranged with a spacing from a portion of the cooling block other than the projection.

Adaptive enabling and disabling is described for valley switching in a power factor correction boost converter. In one example, a boost converter control system includes an amplitude detector to receive an amplitude signal from a boost converter that is related to ringing of the boost converter output. The amplitude detector determines the ringing amplitude. A valley switching controller compares the ringing amplitude to a first high amplitude threshold when valley switching is enabled and generates a valley switching disable signal if the ringing amplitude is below the first high amplitude threshold. A cycle controller coupled to the boost converter generates a drive signal to control switching of the boost converter and coupled to the valley switching controller receives the valley switching disable signal to generate the drive signal without valley switching in response to the valley switching disable signal.

A control circuit for a switching converter, can include: a current compensation signal generating circuit configured to generate a current compensation signal based on a current sampling signal representing an inductor current; and a control signal generating circuit configured to adjust a current control parameter of a current control loop in the switching converter according to the current compensation signal, in order to increase power factor (PF) and reduce total harmonic distortion (THD).