An oscillator circuit includes an oscillator transistor (Q1) having respective first, second, and control terminals, the oscillator transistor being arranged to generate a microwave oscillating signal at the first terminal. A surface integrated waveguide resonator (Y1) is connected to the second terminal of the oscillator transistor (Q1). An active bias circuit portion (202) including a negative feedback arrangement is between the first terminal of the oscillator transistor (Q1) and the control terminal of the oscillator transistor (Q1), the active bias circuit portion being arranged to supply a bias current to the control terminal of the oscillator transistor (Q1). The bias current is dependent on a voltage at the first terminal of the oscillator transistor (Q1) multiplied by a negative gain.

Oscillator circuits, electronic devices, and methods are disclosed. In one embodiment, an oscillator circuit includes a plurality of oscillator transistors comprising a plurality of gates, a plurality of adjustment transistors coupled to the plurality of gates, a differential output coupled to the plurality of oscillator transistors, a plurality of current transistors configured to receive one or more mixed bias current outputs, and generate a main current based on the one or more mixed bias current outputs, the one or more mixed bias current outputs and the main current being substantially constant over a range of temperatures, and one or more switches configured to set an oscillation frequency of the differential output by driving a first portion of a main current through at least one of the plurality of oscillator transistors, and driving a second portion of the main current through at least one of the plurality of adjustment transistors.

Both parallel-type and serial-type dual-mode oscillators employing stress compensated cut resonators having various configurations are disclosed. Both classes of dual-mode oscillators employ multiple tank circuits to pass one frequency of the resonator and block the other frequency. The tank circuits isolate the operation of the two oscillator sub-circuits that form the dual-mode oscillator from one another. The dual-mode oscillators may be implemented with either bipolar or CMOS transistors. The parallel-type dual-mode oscillators employ inverters to provide gain. The serial-type dual-mode oscillators employ a two (or three) stage design including a follower circuit first stage and an inverting amplifier/limiter circuit second stage, with an optional intervening transimpedance amplifier stage.

A two-wire displacement sensor device includes an LC oscillation circuit including a coil whose inductance changes in accordance with a displacement amount of an object and an oscillation unit provided with capacitors and amplifying elements; and an interface unit serving as a signal output unit and a power supply input unit. The interface unit includes a constant current circuit that outputs at least two current values.

Methods and systems for reducing phase noise in a voltage controlled oscillator (VCO) are described. In an example, a first transistor, a second transistor, a third transistor, and a fourth transistor, can be provided. A transformer can be used to decouple drain terminals and gate terminals of the first, second, third, and fourth transistors. An oscillation amplitude of the VCO can be increased by providing a first bias voltage to the transformer to adjust gate bias voltages of the first and second transistors. The oscillation amplitude of the VCO can also be increased by providing a second bias voltage to the transformer to adjust gate bias voltages of the third and the fourth transistors.

A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.

Methods and systems for reducing phase noise in a voltage controlled oscillator (VCO) are described. In an example, a first transistor, a second transistor, a third transistor, and a fourth transistor, can be provided. A transformer can be used to decouple drain terminals and gate terminals of the first, second, third, and fourth transistors. An oscillation amplitude of the VCO can be increased by providing a first bias voltage to the transformer to adjust gate bias voltages of the first and second transistors. The oscillation amplitude of the VCO can also be increased by providing a second bias voltage to the transformer to adjust gate bias voltages of the third and the fourth transistors.

An ultra-low noise crystal oscillator uses two crystal unit; an oscillation element of an oscillation circuit section and a crystal filter of a subsequent filter section. A Butler circuit in which the capacitors (C1, C2) and the inductor (L) connected in series is connected in parallel to the oscillator circuit section. This is the crystal oscillator that simplifies the manufacturing process, improves the manufacturing quality, and has good floor noise characteristics.

An ultra-low noise crystal oscillator uses two crystal unit; an oscillation element of an oscillation circuit section and a crystal filter of a subsequent filter section. A Butler circuit in which the capacitors (C1, C2) and the inductor (L) connected in series is connected in parallel to the oscillator circuit section. This is the crystal oscillator that simplifies the manufacturing process, improves the manufacturing quality, and has good floor noise characteristics.

A frequency synthesizer (230) is described that includes: a voltage controlled oscillator, VCO (330); a VCO bias circuit (370), operably coupled to the VCO (330) and configured to provide a controllable bias current (384) of the VCO (330); a temperature sensor (372) located in the frequency synthesizer (230) and configured to determine an operating temperature of the frequency synthesizer (230); an analog-to-digital converter, ADC (376), operably coupled to the temperature sensor (372) and configured to provide a digital representation (378) of the determined operating temperature; and a bias control circuit (380) operably coupled to the ADC (376) and the VCO bias circuit (370) and configured to provide a bias control signal (382) to the VCO bias circuit (370) based on the determined operating temperature of the frequency synthesizer (230). The VCO bias circuit (370) is configured to adjust the controllable bias current (384) applied to the VCO based on the bias control signal (382). The frequency synthesizer (230) includes a digitally-controlled bias current adjustment method for a wideband low noise VCO, for example using idle time intervals of signal transitions.