A frequency multiplier includes an input section having inputs to receive an input signal having an input frequency, a mixer section, and an output section magnetically coupled to the input section and generating an output signal in response to the input signal. The mixer section may be coupled to the input section by a common mode node forming a path for a common mode current to flow to the mixer section and be magnetically coupled to the common mode node. The input section may generate a signal current, and the mixer section may be magnetically coupled to the input section and be directly capacitively coupled to the input section through a capacitor in a signal current path. The mixer section may have differential inputs capacitively coupled to the input section and also be coupled to the input section through a current path. A current helper section may be coupled to the current path.

A processor may calibrate a first actuator electrically coupled to a transconductance stage of the frequency conversion circuit. The transconductance stage may be configured to receive a differential signal input. Calibrating a first actuator may adjust a first basis vector associated with a differential direct current (DC) output of the transconductance stage. A processor may calibrate a second actuator electrically coupled to receive the differential current output of the transconductance stage and electrically coupled to a set of commutating devices of the frequency conversion circuit. The commutating devices may be configured to receive differential LO inputs. Calibrating a second actuator may adjust a second basis vector associated with a differential impedance of the set of commutating devices. A processor may offset responsive to adjusting the first basis vector and the second basis vector, the first leakage basis vector and second leakage basis vector of the LO leakage signal.

A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.

Embodiments of communications devices and methods for operating a communications device are described. In an embodiment, a communications device includes a complex multiplier configured to multiply a first input complex signal with a second input complex signal to generate an output complex signal, an amplifier configured to amplify an imaginary part of the output complex signal to generate an amplification result, a delay element configured to delay a rotation angle signal that is related to the second input complex signal, and a subtractor configured to subtract the amplification result from the delayed rotation angle signal to generate the rotation angle signal. Other embodiments are also described.

Multi-input downconversion mixers, systems, and methods are provided with input switching in the intermediate frequency or baseband domain. One illustrative mixer embodiment includes: multiple differential pairs of transistors and multiple pairs of switches. Each differential transistor pair has their bases or gates driven by a differential reference signal, their emitters or sources connected to a common node having a current or voltage driven based on a respective one of multiple receive signals, and their collectors or drains providing a product of the differential reference signal with the respective one of the multiple receive signals. Each of the switch pairs selectively couples differential output nodes to the collectors or drains of a respective one of the multiple differential pairs, enabling the differential output nodes to convey an output signal that is a sum of products from selected ones of the multiple differential pairs.

A biasing scheme for a frequency multiplication circuit, and transceiver using LO signals provided by the frequency multiplication circuit are described. A frequency doubler is cascaded with a mixer to provide a mm-wave oscillator signal. The combination provides a frequency triple that of the LO frequency supplied to the frequency doubler from a PLL. A small-sized replica of the frequency doubler is used to determine biasing of transconductance devices of the frequency doubler. A voltage output of the replica is amplified and the difference between the output and a reference voltage is supplied as feedback to the control terminal of the transconductance devices to bias the transconductance devices to near threshold. The biasing is replicated at the frequency doubler to compensate for PVT variations. A PTAT current source tied to the output of the replica regulates an average output current of the frequency multiplication circuit.

A travelling wave mixer (TWM) is provided that includes an input artificial transmission line configured to transmit an input signal, an output artificial transmission line configured to transmit an output signal, a local oscillator (LO) artificial transmission line configured to transmit an LO signal, and a plurality of mixer stages connected in parallel between the output artificial transmission and the input artificial transmission line. Each of the mixer stages includes an input amplifier, a mixer and an output amplifier connected in series between the input artificial transmission line and the output artificial transmission line, where an input of the mixer receives an output of the input amplifier, and an output of the mixer is applied to an input of the output amplifier. Further, each of the mixer stages includes a phase-adjustable LO amplifier circuit connected between the LO artificial transmission line and an LO input of the mixer, where the phase-adjustable LO amplifier is configured to adjust an LO signal phase applied to the LO input of each mixer to null out a phase error in each mixer stage independently.

Multi-input downconversion mixers, systems, and methods are provided with input switching in the intermediate frequency or baseband domain. One illustrative mixer embodiment includes: multiple differential pairs of transistors and multiple pairs of switches. Each differential transistor pair has their bases or gates driven by a differential reference signal, their emitters or sources connected to a common node having a current or voltage driven based on a respective one of multiple receive signals, and their collectors or drains providing a product of the differential reference signal with the respective one of the multiple receive signals. Each of the switch pairs selectively couples differential output nodes to the collectors or drains of a respective one of the multiple differential pairs, enabling the differential output nodes to convey an output signal that is a sum of products from selected ones of the multiple differential pairs.

A frequency multiplier includes an input section to receive a quadrature phase input signal having an input frequency, a mixer section coupled to the input section by a common mode node that forms a path for the common mode signal current to flow to the mixer section and magnetically coupled to the common mode node or capacitively coupled to the input section to generate a differential switching voltage at odd multiples of twice the input frequency, which switching voltage is applied to inputs of the mixer section, and an output section magnetically coupled to the mixer section, the output section being configured to generate an output voltage having a dominate frequency and sub-dominate frequencies spaced apart by the first multiple, the dominate frequency of the output voltage being a second multiple of the input frequency, where the second multiple is greater than the first multiple. Various arrangements are provided.

A distributed amplifier includes a first transmission line for input, a second transmission line for output, an input termination resistor connecting a line end of the first transmission line and a power supply voltage, an output termination resistor connecting an input end of the second transmission line and a ground, unit cells having input terminals connected to the first transmission line and output terminals connected to the second transmission line, and a bias tee configured to supply a bias voltage to an input transistor of each of the unit cells. An emitter or source resistor of the input transistor of each of the unit cells is set to a different resistance value from each other in order for a collector or drain current flowing through the input transistor of each of the unit cells to have a uniform value.