Various embodiments disclosed herein enable steerable, time division duplex (“TDD”) communications channels at millimeter-wave frequency bands. Among other things, embodiments disclosed herein provide improved steering accuracy and power distribution, lower power consumption, and potentially longer service life than previous transceiver systems.

A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.

A configurable passive mixer is described herein. According to one exemplary embodiment, a passive mixer for a wireless receiver comprises a plurality of passive mixer cores coupled in parallel with each mixer core configured to receive a same set of radio frequency input signals and a separately driven set of local oscillator input signals. Further, each mixer core is configured to be separately enabled or disabled so that the passive mixer can be selectively configured during operation to convert the same set of radio frequency input signals to a set of downconverted output signals that satisfy a certain performance requirement or performance parameter of the passive mixer.

A combined mixer and filter circuitry is disclosed. The combined mixer and filter circuitry comprises a mixer comprising a first input, a second input and an output. The combined mixer and filter circuitry further comprises a filter comprising an active inductor and a first capacitor. The active inductor comprises a transistor having a first terminal, a second terminal and a third terminal and a resistor connected between the first terminal of the transistor and a voltage potential. The first capacitor is connected between the third terminal and a signal ground and the second terminal of the transistor is connected to the second input of the mixer.

To provide a mixer and a semiconductor device which each have a small circuit area and each of which operation capability is inhibited from being decreased due to heat. The mixer includes a differential portion, a current source, a first load, an input terminal, and a first output terminal; the differential portion includes a first and a second transistor; and each of the first and the second transistors includes a metal oxide in a channel formation region. A first terminal of each of the first and the second transistors is electrically connected to the input terminal and a current source and a second terminal of the first transistor is electrically connected to a first terminal of the first load and the first output terminal. The first load has a function of supplying a current between the first terminal and a second terminal of the first load by application of voltage to the second terminal of the first load, and the current source has a function of supplying a constant current to the current source from the first terminal of each of the first and the second transistors. The current source includes a transistor including silicon in a channel formation region, and the differential portion is positioned above the current source.

A transmitter that reduces 3.sup.rd order harmonic (HD3) and inter modulation distortion (IMD3) for a gm stage of a mixer while reducing flicker noise is disclosed. The transmitter may include a balanced mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include a programmable current source configured to provide a reference current. Further, the bias circuit may include a replica circuit configured to replicate a DC signal of the transconductance stage. The bias circuit may also include a bias transistor configured to level shift a bias signal obtained from a signal source based on the reference current and the DC signal of the transconductance stage as determined from the replica circuit.

The present disclosure discloses a harmonic rejection mixing circuit device and a receiver. In the harmonic rejection mixing circuit device, outputs of first and fourth mixers are combined with the input terminal of the fourth mixer being connected to a capacitor, the first mixer samples a first group of local oscillator (LO) signals, and the fourth mixer phase-invertedly samples the first group of LO signals, thus the noise introduced by a fundamental LO signal input to the first mixer may be eliminated using the double balance feature of the fourth mixer core, thereby ensuring a high signal-to-noise ratio of the receiver. Similarly, the noises introduced by fundamental LO signals input to second and third mixers may be eliminated respectively using the double balance features of the fifth and sixth mixer cores, thereby lowering the noise figure to ensure a high signal-to-noise ratio of the receiver.

Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.