An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.

A receiver includes one or more mixers configured to sample an input analog signal at a plurality of discrete points in time to obtain a discrete-time sampled signal based on a local oscillating signal provided by a local oscillator; and a sample reordering circuit coupled to the one or more mixers and configured to reorder a sequence of samples received from the one or more mixers.

A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a V.sub.EE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.

A multi-mode processing circuit and a multi-mode controlling method thereof are provided. The multi-mode processing circuit includes, but is not limited to, a control circuit and a mixer. The control circuit is configured to receive an input signal and output one of a control signal and another control signal according to the input signal. The mixer is coupled to the control circuit and is configured to mix the control signal output by the control circuit with another input signal or mix the other control signal with the another input signal to output an output signal. Accordingly, the mixer and a buffer can be integrated into a single cell, and a fast mode switch can be achieved.

A receiver circuit is provided. The receiver circuit includes an antenna configured to receive a radio frequency (RF) signal; a filter configured to filter the RF signal received by the antenna; and a passive mixer circuit configured to adjust a center frequency of the filtered RF signal to a predetermined frequency. The passive mixer circuit includes: a transformer which includes a first coil and a second coil that is separate from the first coil; a first passive mixer which is directly connected to a first end of the second coil; and a second passive mixer which is directly connected to a second end of the second coil and is separate from the first passive mixer.

A capacitor circuit includes a first terminal, a first to a third transistor and a first capacitor. The first transistor includes a first terminal configured to be coupled to a first current source and the first terminal of the capacitor circuit, and a second terminal coupled to a reference voltage terminal. The second transistor includes a first terminal configured to be coupled to a second current source, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the first terminal of the second transistor and a control terminal of the first transistor. The third transistor includes a first terminal configured to be coupled to a third current source and the first terminal of the first transistor, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the control terminal of the second transistor. The first capacitor includes a first terminal coupled to the first terminal of the capacitor circuit, and a second terminal coupled to the control terminal of the first transistor.

A mobile terminal including an up-converter converting a baseband (BB) signal into a radio frequency (RF) signal and a controller controlling a voltage applied to the up-converter is provided. The up-converter includes a first transistor and a second transistor each having a gate to which a baseband voltage is applied, a third transistor having a drain connected in parallel to a drain of the first transistor, and a fourth transistor having a drain connected in parallel to a drain of the second transistor, and the up-converter and the mobile terminal with improved phase linearity characteristics may be provided.

A unit cell for a resistive mixer includes a plurality of active devices arranged in series, wherein each of said plurality of active devices having a different output conductance. A resistive mixer includes a plurality of active devices connected in series with one another to form a unit cell.

A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Certain aspects provide a circuit for frequency conversion. The circuit includes first mixer circuitry coupled to a load circuit and having a first mixer configured to generate a first portion of a frequency-converted differential signal to be provided to the load circuit based on first differential input signals and second differential input signals, and a second mixer configured to generate a second portion of the frequency-converted differential signal based on third differential input signals and fourth differential input signals. The circuit also includes second mixer circuitry coupled to another load circuit and having a third mixer configured to generate a first portion of another frequency-converted differential signal based on the first differential input signals and the fourth differential input signals, and a fourth mixer configured to generate a second portion of the other frequency-converted differential signal based on the third differential input signals and the second differential input signals.