The present invention discloses a mixer bias circuit including a first reference voltage generation circuit, an amplifier, a first transistor array, a first switch array, a second reference voltage generation circuit, a second transistor array, a second switch array, a first resistive component, and a second resistive component. The mixer bias circuit provides multiple bias voltages by dynamically tracking the common mode voltage of a trans-impedance amplifier (TIA) and compensates for imbalance and mismatch effects by asymmetrically trimming the bias voltages to improve the second-order intercept point of a radio frequency (RF) receiver front-end (RXFE).

A wireless receiving device is provided. The wireless receiving device includes a first passive mixer and a common gate amplifier. The first passive mixer receives an oscillation signal. The common gate amplifier is coupled to the first passive mixer, and automatically adjusts the input impedance of the common gate amplifier according to the oscillation frequency of the oscillation signal.

A circuit comprising: a first passive mixer (21) having mixer inputs configured to receive in-phase (I) and quadrature-phase (Q) differential signals; and a first differential sub-circuit (31). The first passive mixer is configured to switch the in-phase (I) and quadrature-phase (Q) differential signals to the first differential sub-circuit at a mixing frequency. The first differential sub-circuit (31) has a pair of differential inputs configured to receive the switched in-phase (I) and quadrature-phase (Q) differential signals from the first passive mixer (21), each input having a capacitance capable of storing a charge that depends on the switched in-phase or quadrature-phase signals. The circuit further comprises a charge canceller configured to supply, to at least one of: the mixer inputs; and the pair of differential inputs, an opposite charge compared with a charge that has been stored on the pair of differential inputs by the operation of the first passive mixer.

Systems and methods are disclosed for compensating local oscillator leakage in a mixer. An example mixer includes a first double-balanced mixer core and a second double-balanced mixer. The first double-balanced mixer may comprise differential output nodes and may be configured to mix a first input signal with a first local oscillator signal. The second double-balanced mixer core may comprise second differential output nodes and may be configured to mix a second input signal with a second local oscillator signal. The second input signal may be approximately 180 out of phase with the first input signal. The second local oscillator signal may be approximately 180 out of phase with the first local oscillator signal. The differential output nodes may be electrically connected to the second differential output nodes, and the first double-balanced mixer core and the second double-balanced mixer core may be arranged to compensate for local oscillator leakage.

A radio frequency (RF) mixer is provided. The RF mixer includes two linear-in-the-amplitude-domain RF channels connected in parallel, with each of the two linear-in-the-amplitude-domain RF channels having of an input RF signal applied equally to each channel. Two controllable gain devices are structured to receive the input RF signal. A local oscillator (LO) communicates with both of the controllable gain devices, with one of the controllable gain devices receiving a signal from the LO directly, and the other controllable gain device receiving a signal from the LO after a phase of the LO signal is reversed by a phase inverter. Finally, an output of each of the linear-in-the-amplitude-domain RF channels is combined to form a common intermediate frequency (IF) output.

In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.

Circuits comprising: a plurality of LNTA branches, each comprising: a cascode common-source (CCS) LNTA, a plurality of passive mixers (PMs), and a plurality of baseband two-stage Miller compensated TIAs (BB2S-TIAs); a plurality of mixer-first branches, each comprising: a plurality of RF switches, a plurality of baseband folded-cascode TIAs (BBFC-TIAs), and a plurality of Cherry-Hooper amplifiers, wherein an input to each of the BBFC-TIAs is provided by an output of at least one of the RF switches, and an input to each of the amplifiers is provided by an output of a corresponding one of the BBFC-TIAs; a first plurality of clock modulators that provide first non-overlapping modulated clocks that are provided to an input of the PMs; and a second plurality of clock modulators that provide a plurality of tri-level modulated mixer clocks that control the switching of the RF switches.

A radio receiver device is arranged to receive an input voltage signal at an input frequency and comprises: a first amplification circuit portion; a second amplification circuit portion; a current buffer circuit portion; and a down-mixer circuit portion. The first amplification circuit portion is arranged to amplify the input voltage signal to generate an amplified current signal which is input to the current buffer circuit portion. The current buffer circuit portion has an input impedance and an output impedance, wherein the output impedance is greater than the input impedance and is arranged to generate a buffered current signal. The down-mixer circuit portion is arranged to receive the buffered current signal and generate a down-converted current signal at a baseband frequency. The second amplification circuit portion is arranged to amplify the down-converted current signal to produce an output voltage signal.

Systems and methods are disclosed for improved linearity performance of a mixer. An example mixer includes switching circuit elements configured to be switched on and switched off based at least partly on a local oscillator signal and capacitors including a respective capacitor in parallel with each of the switching elements. The mixer is configured to mix the input signal with the local oscillator signal to thereby frequency shift the input signal.

Systems, methods, and circuitries are provided for a local oscillator (LO) signal distribution. An exemplary LO distribution network includes a common LO buffer configured to buffer an LO signal, a receive (RX) LO buffer, and a transmit (TX) mixer in a cascaded arrangement. The RX LO buffer is configured to receive the LO signal and buffer the LO signal and to provide the LO signal to an RX mixer. A first LO signal line and a second LO signal line are configured to conduct the LO signal from the common LO buffer to the RX LO buffer. The RX LO buffer is coupled to the first LO signal line and the second LO signal line. The TX mixer is also coupled to the first LO signal line and the second LO signal line.