Techniques that facilitate reconfigurable transmission of a radar frequency signal are provided. In one example, a system includes a signal generator and a power modulator. The signal generator provides a radar waveform signal from a set of radar waveform signals. The power modulator divides a local oscillator signal associated with a first frequency and a first amplitude into a first local oscillator signal and a second local oscillator signal. The power modulator also generates a radio frequency signal associated with a second frequency and a second amplitude based on the radar waveform signal, the first local oscillator signal and the second local oscillator signal.

A mixer termination circuit for a downconverter mixer includes a diplexer circuit coupled to an output of the downconverter mixer. The diplexer circuit is configured to separately terminate a sum component present in an output signal of the downconverter mixer and a difference component present in the output signal of the downconverter mixer.

Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signals separated in phase by a constructed amount of phase based on the specified mixing ratio. Additional apparatus, systems, and methods are disclosed.

An integrated circuit that selectively filters out common-mode and differential signals is described. This integrated circuit may include an RF receiver with a mixer that converts signals between a band of frequencies in the RF and a second band of frequencies based at least in part on second signals, where the second band of frequencies is less than the band of frequencies. Moreover, the mixer may include input ports that receive the second signals and include a filter circuit, electrically coupled in parallel with the input ports, that filters out the common-mode signals above a threshold frequency and filters out the differential signals below the threshold frequency. For example, the filter circuit may include a half-wavelength transmission line. Note that the mixer may convert the differential signals to the common-mode signals below the threshold frequency and may convert the common-mode signals to the differential signals above the threshold frequency.

A down-conversion mixer includes a transconductance unit, a resonant unit and a mixing unit. The transconductance unit converts a differential input voltage signal pair into a differential input current signal pair. The resonant unit provides a negative resistance and a differential auxiliary current signal pair. The mixing unit mixes a combination of the differential input current signal pair and the differential auxiliary current signal pair with a differential oscillatory voltage signal pair to generate a differential mixed voltage signal pair.

An equalizer circuit includes an phase-to-phase connectors including an phase-to-phase capacitor and four phase-to-phase switches, four output buffers, and control signal generation circuitry. One terminal of each phase-to-phase switches is connected to one of four connection paths on which four conversion signals being different in phase by 90 are input. The other one terminal of each phase-to-phase switches is connected to the phase-to-phase capacitor. Each output buffer is connected to one of the four connection paths and outputs an output signal. The control signal generation circuitry outputs control signals to control turning-on/off of the respective four phase-to-phase switches. A closing of the first, second, third, and fourth phase-to-phase switches are started from any one of phase-to-phase switches in one of a first ascending circulation and a first descending circulation based on the 4-phase control signals.

A SSB (single sideband) mixer is configured to mix a first signal with a second signal, both the first signal and the second signal being a four-phase signal, and comprises eight gated inverters, each receiving a respective phase of the first signal and conditionally outputting a respective current in accordance with a control of a respective phase of the second signal, wherein currents output from the eight gated inverters are summed to establish a third signal that is a two-phase signal.

A clock generator has a buffer stage circuit, a passive mixer, and a channel selecting circuit. The buffer stage circuit receives a plurality of first reference clocks having a same first frequency but different phases. The passive mixer receives the first reference clocks from the buffer stage circuit, receives a plurality of second reference clocks having a same second frequency but different phases, and mixes the first reference clocks and the second reference clocks to generate a mixer output, wherein the second frequency is different from the first frequency. The channel selecting circuit extracts a plurality of third reference clocks from the mixer output, wherein the third reference clocks have a same third frequency but different phases, and the third frequency is different from the first frequency and the second frequency.

An apparatus and a method. The apparatus includes passive mixers, wherein each of the passive mixers includes a first input for receiving BB.sub.I, a second input for receiving BB.sub.I, a third input for receiving BB.sub.Q, a fourth input for receiving BB.sub.Q, a fifth input for receiving a first clock signal with a unique phase shift within one of the passive mixers, a sixth input for receiving a second clock signal with a unique phase shift within one of the passive mixers, a seventh input for receiving a third clock signal with a unique phase shift within one of the passive mixers, an eighth input for receiving a fourth clock signal with a unique phase shift within one of the passive mixers, and at least one output; and a voltage-domain vector summation array connected to the output of each of the passive mixers.

An apparatus and a method. The apparatus includes passive mixers, wherein each of the passive mixers includes a first input for receiving BB.sub.I, a second input for receiving BB.sub.I, a third input for receiving BB.sub.Q, a fourth input for receiving BB.sub.Q, a fifth input for receiving a first clock signal with a unique phase shift within one of the passive mixers, a sixth input for receiving a second clock signal with a unique phase shift within one of the passive mixers, a seventh input for receiving a third clock signal with a unique phase shift within one of the passive mixers, an eighth input for receiving a fourth clock signal with a unique phase shift within one of the passive mixers, and at least one output; and a voltage-domain vector summation array connected to the output of each of the passive mixers.