A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

An input driver includes a power converting unit and a level adjusting unit. The power converting unit is configured to generate a first power and a second power having an anti-phase relationship based on input power, and process the first power and the second power as differential inputs to output a third power. The level adjusting unit is configured to adjust a voltage level of the third power and output the adjusted power as an input to a power amplifier.

An compensation circuit for an Amplitude Modulation-Amplitude Modulation (AM-AM) of a Radio Frequency (RF) power amplifier, including: a first biasing circuit, a power amplifier, and a compensation circuit located between the first biasing circuit and the power amplifier; herein, the compensation circuit includes a diode detection circuit and a feedforward amplifier for compensating AM-AM distortion.

Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

The present disclosure relates to circuitry including an auto-bias circuit for a stacked FET power amplifier. The auto-bias circuit includes a dividing circuit and an averaging circuit. The dividing circuit is configured to receive a control signal with a control voltage and provide a first pre-gate signal having a first pre-gate voltage that corresponds to a fraction of the control voltage. The averaging circuit is configured to receive the control signal and a supply signal with a supply voltage and provide a second pre-gate signal having a second pre-gate voltage that corresponds to a fraction of a sum of the control voltage and the supply voltage. The stacked power amplifier includes a first FET in series with a second FET. The first FET receives a first gate signal derived from the first pre-gate signal. The second FET receives a second gate signal derived from the second pre-gate signal.

A bias circuit is adapted for biasing a to-be-biased transconductance cell such that the to-be-biased transconductance cell has a constant transconductance, and includes a converter and a controller. The converter receives first and second current signals, and generates, based on the first and second current signals, a first voltage signal, a second voltage signal and a bias voltage that is for biasing the to-be-biased transconductance cell. The controller receives the first and second voltage signals from the converter, generates the first and second current signals for the converter based on the first and second voltage signals so as to make a magnitude of the first voltage signal equal a magnitude of the second voltage signal.

A direct current (DC)-DC converter that includes a first switching converter and a multi-stage filter is disclosed. The multi-stage filter includes at least a first inductance (L) capacitance (C) filter and a second LC filter coupled in series between the first switching converter and a DC-DC converter output. The first LC filter has a first LC time constant and the second LC filter has a second LC time constant, which is less than the first LC time constant. The first LC filter includes a first capacitive element having a first self-resonant frequency, which is about equal to a first notch frequency of the multi-stage filter.

A power switch 307a is provided between a bias generation circuit 301 and a high potential power source, or a power switch 307b is provided between the bias generation circuit 301 and a low potential power source. A bias potential Vb output from the bias generation circuit 301 is held by a potential holding circuit 300. The bias potential Vb held by the potential holding circuit 300 is input to a bias generation circuit 301a, and a bias potential Vb2 output from the bias generation circuit 301a on which an input signal IN is superimposed is input to an amplifier circuit 302. The potential holding circuit 300 is constituted of a capacitor 306 and a switch 305 formed of, for example, a transistor with a low off-state current that is formed using a wide band gap oxide semiconductor. Structures other than the above structure are claimed.

A temperature correction circuit and method for maintaining a transistor of a power amplifier in a linear operating region of the transistor. The temperature correction circuit includes a first current source circuit operable to provide a first correction current proportional to an absolute temperature of a semiconductor die including the transistor. The temperature correction circuit also includes a second current source circuit operable to provide a second correction current proportional to a change in temperature of a part of the semiconductor die in which the transistor is located during operation of the transistor. The temperature correction circuit further includes a third current source circuit operable to provide a gain selection current. The temperature correction circuit also includes circuitry for producing a reference current from the first and second correction currents and the gain current. The temperature correction circuit further includes an output for providing the reference current to the transistor.

A charge pump circuit having first and second input nodes to be coupled to a first power source, and top and bottom output nodes and an intermediate node. The charge pump circuit produces i) a voltage at the top output node that is higher than a voltage of the intermediate node, and ii) a voltage at the bottom output node that is lower than the voltage of the intermediate node. A bias voltage source has i) an input that is to be coupled to a second power source and ii) an output that produces an output voltage, which is a predetermined proportion of an input voltage at the input and that follows the input voltage downward and upward as the input voltage sags and recovers, respectively. The output of the bias voltage source is directly connected to the intermediate node of the output stage. Other embodiments are also described.