An RF power detector adapted to detect an RF power of an RF signal, includes, in part, an antenna adapted to receive the RF signal, a narrow-band RF power converter adapted to convert the RF signal to a DC signal, an accelerometer, and a magnetometer. The accelerometer and magnetometer are adapted to determine the orientation and location of the power detector. The power detector optionally includes a gyroscope. The narrow-band RF power converter may be a rectifier tuned to the frequency of the RF signal. The power detector optionally includes an indicator adapted to provide information representative of the amount of the DC power of the DC signal, as well as position and orientation of the power detector. The power detector may be adapted to be inserted into a mobile device so as to provide the information about the amount of DC power, orientation and position to the mobile device.

A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.

Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.

Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

An amplification circuit includes a filter circuit, an amplifier, a capacitor, a bypass line, and a switch circuit that includes a first FET and a second FET connected in series between one end and the other end of the bypass line, a first resistance element connected in series to a gate of the first FET, and a second resistance element connected in series to a gate of the second FET. A first control signal is supplied to the gate of the first FET. A second control signal is supplied to the gate of the second FET. A product of a gate length and a gate width of the first FET and a resistance value of the first resistance element is smaller than a product of a gate length and a gate width of the second FET and a resistance value of the second resistance element.

A Class-D amplifier that includes a driver stage operable in a plurality of modes having different respective output impedances, a loop filter having an output, and a circuit configured to sense a current at a load of the Class-D amplifier, determine, based on the sensed current, an IR drop for a respective output impedance of the driver stage, and add the IR drop to the loop filter output to compensate for the respective output impedance of the driver stage to reduce distortion.

According to one embodiment, a class-D amplifier including: a PWM modulator that outputs a PWM modulation signal in response to an input signal; and a drive circuit that amplifies the PWM modulation signal, and supplies it to an output end. The drive circuit includes: a first output transistor whose main current path is connected between a power source supplying end and the output end; a second output transistor having a size larger than a size of the first output transistor; and a resistance element that is connected between the main current path of the first output transistor and the output end.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

A signal processing system includes n paths of load modulation modules and a combination module, where then paths of load modulation modules are connected in parallel, an output end of each path of load modulation module is connected to an input end of the combination module, and n is an integer greater than 1; the n paths of load modulation modules include one path of main power amplification module and (n-1) paths of auxiliary power amplification modules, and the auxiliary power amplification modules are turned on when power values of signals received by input ends of the load modulation modules are greater than a first threshold; and the main power amplification module includes two outphasing power amplification units, and each path of auxiliary power amplification module includes two outphasing power amplifier arrays or one digital polar power amplifier array.

A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.