Patent classifications
H03F1/0277
METHOD OF OPERATING AN N-WAY POWER COMBINER NETWORK AND AN N-WAY POWER COMBINER NETWORK
Method of operating a power combiner network (1), the power combiner network (1) comprising a power combiner device (10) having N secondary ports (11(1, 2, N)) combining into one primary port (12), wherein respective N secondary port (11(1, 2, . . . , N)) is provided with a phase shifter arrangement (13) and a load control arrangement (14). Respective phase shifter arrangement (13) is configured to set a phase of a signal fed through respective N secondary port (11(1, 2, . . . , N)). Respective load control arrangement (14) is configured to set the N secondary ports (11(1, 2, . . . , N)) in an active or in an inactive operation mode. For I inactive secondary ports (11(1)) the load control arrangement (14) is further configured to set a phase of the signal reflected from the I inactive secondary ports (11(1)). The method comprises the method steps of; step A (100), selecting which of the N secondary ports (11(1, 2, . . . , N)) that should be set in an inactive operation mode and which of the N secondary ports (11(1, 2, . . . , N)) that should be set in an active operation mode, step B (110), setting selected I inactive secondary ports (11(1)) in an inactive operation mode by means of the load control arrangement (14), step C (120), retrieving a phase required for respective I inactive secondary port (11(1)) and retrieving a phase required for respective A active secondary port (11(2)) in order for respective A active secondary port (11(2)) to minimize the reflected signal from the power combiner device (10) and provide desired power to the primary port (12), step D (130), setting respective load control arrangement (14) for respective I inactive secondary port (11(1)) according to respective retrieved phase, and step E (140), setting respective phase shifter arrangement (13) for respective A active secondary port (11(2)) according to respective retrieved phase.
APPARATUS AND METHOD FOR AMPLIFYING TRANSMISSION SIGNALS IN WIRELESS COMMUNICATION SYSTEM
The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long term evolution (LTE). The present disclosure is to amplify transmission signals in a wireless communication system, and a transmitting device may include an antenna array including a plurality of antenna elements, a plurality of amplification chains for amplifying signals transmitted through the plurality of the antenna elements, and a power supply line for supplying powers to the plurality of the amplification chains. Herein, the powers used by power amplifiers included in at least one amplification chain of the plurality of the amplification chains may be divided by filtering or by independent pads and branch-lines.
Amplifier circuit
An amplifier circuit includes an output terminal, an amplification unit and a switch. The output terminal is used to output an amplification signal. The amplification unit includes a first transistor and a second transistor. The first transistor includes a control terminal for receiving a first input signal, a first terminal coupled to the output terminal for outputting an amplified first input signal, and a second terminal. The second transistor includes a control terminal for receiving a second input signal, a first terminal coupled to the output terminal for outputting an amplified second input signal, and a second terminal. The switch includes a first terminal coupled to the second terminal of the first transistor, and a second terminal. The amplification signal is generated using at least the amplified first input signal and/or the amplified second input signal.
INTEGRATED CIRCUIT DEVICES WITH PARALLEL POWER AMPLIFIER OUTPUT PATHS
An integrated circuit device is provided. In some examples, the integrated circuit device includes a first amplifier path, a second amplifier path coupled in parallel with the first amplifier path, a matching network coupled to the first amplifier path and the second amplifier path, and an antenna coupled to the matching network. In some such examples, the first amplifier path includes a first differential power amplifier coupled to the matching network, and the second amplifier path includes a second differential power amplifier coupled to the matching network. The integrated circuit device may further include a controller coupled to selectively enable the first amplifier path to provide a transmitter output power within a first range and to selectively enable the second amplifier path to provide a transmitter output power within a second range that is different from the first range.
POWER AMPLIFIER CIRCUIT
A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs an output signal; a second amplifier that, in accordance with a control signal, amplifies a signal corresponding to the input signal, generates a signal having an opposite phase to that of the output signal, and adds the signal to the output signal; and a control circuit that supplies the control signal to the second amplifier. The control circuit outputs the control signal so that during operation of the power amplifier circuit in a first power mode, a gain of the second amplifier is not less than zero and less than a predetermined level and during operation in a second power mode lower than the first power mode in output power level, a gain of the second amplifier is not less than the predetermined level and less than a gain of the first amplifier.
Single-wire peer-to-peer bus
A single-wire peer-to-peer (P2P) bus apparatus is provided. The single-wire P2P bus apparatus includes a first peer device and a second peer device(s) coupled to a single-wire bus that correspond to a first bus access priority and a second bus access priority(s), respectively. Any of the first peer device and the second peer device(s) can contend for access to the single-wire bus by asserting a bus contention indication(s) when the single-wire bus is in a defined bus state. A winner for the single-wire bus may be a peer device having a highest bus access priority among those peer devices asserting the bus contention indication(s). In this regard, any peer device on the single-wire bus can have a chance to initiate communications over the single-wire bus, thus making it possible for the single-wire bus to function based on bidirectional P2P bus architecture capable of supporting more application and/or deployment scenarios.
Integrated circuit devices with parallel power amplifier output paths
An integrated circuit device is provided. In some examples, the integrated circuit device includes a first amplifier path, a second amplifier path coupled in parallel with the first amplifier path, a matching network coupled to the first amplifier path and the second amplifier path, and an antenna coupled to the matching network. In some such examples, the first amplifier path includes a first differential power amplifier coupled to the matching network, and the second amplifier path includes a second differential power amplifier coupled to the matching network. The integrated circuit device may further include a controller coupled to selectively enable the first amplifier path to provide a transmitter output power within a first range and to selectively enable the second amplifier path to provide a transmitter output power within a second range that is different from the first range.
Multi-amplifier envelope tracking circuit and related apparatus
A multi-amplifier envelope tracking (ET) circuit and related apparatus are provided. The multi-amplifier ET circuit includes a number of amplifier circuits configured to amplify concurrently a radio frequency (RF) signal to generate a number of amplified RF signals for concurrent transmission, for example, in a millimeter wave (mmWave) spectrum. The amplifier circuits are configured to amplify the RF signal based on a number of ET voltages and a number of low-frequency currents, respectively. A number of driver circuits is provided in the multi-amplifier ET circuit to generate the ET voltages and the low-frequency currents for the amplifier circuits, respectively. In examples discussed herein, the driver circuits are co-located with the amplifier circuits to help improve efficiency and maintain linearity in the amplifier circuits, particularly when the RF signal is modulated at a higher modulation bandwidth (e.g., >80 MHz).
ULTRA COMPACT MULTI-BAND TRANSMITTER WITH ROBUST AM-PM DISTORTION SELF-SUPPRESSION TECHNIQUES
A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
High-frequency signal processing apparatus and wireless communication apparatus
A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.