An amplifier for driving a display panel includes an input stage, a gain stage and an output stage. The gain stage is coupled to the input stage. The output stage, coupled to the gain stage, includes a first output driving circuit and a second output driving circuit. The first output driving circuit is operated in a first voltage domain. The second output driving circuit is operated in a second voltage domain different from the first voltage domain.

A bias circuit for a Doherty amplifier, characterized by comprising: an input port with an input impedance, wherein the input port is configured to receive a bias signal from a power supply; a first output port configured to provide a bias signal to an amplifier; a second output port configured to provide a bias signal to an amplifier; a two port impedance transformer with an input connected to the first input port, and an output of the two port impedance transformer having an intermediate impedance; an in-phase N-port dividing impedance transformer with an input connected to the output of the two port impedance transformer, wherein the in-phase N-port dividing impedance transformer comprises: a first output connected to the first output port having a first output impedance; and a second output connected to the second output port having a second output impedance.

A bidirectional bipolar transistor switch arrangement, including: a first bipolar transistor and a second bipolar transistor connected in anti-parallel between a first terminal and a second terminal, a resistor connected to the base of the first bipolar transistor and the second bipolar transistor and to a control terminal, a first diode connected with anode to the first terminal, a second diode connected with anode to the second terminal, the first diode and the second diode being connected via respective cathodes to a supply terminal.

The bidirectional bipolar transistor switch arrangement is able to control the power supply within a daisy chain with low drop voltage.

A power amplifier apparatus is provided. The power amplifier apparatus includes a number of multi-stage power amplifiers and a bias circuit configured to generate a number of bias signals (e.g., bias current or bias voltage) to control (e.g., activate or deactivate) the multi-stage power amplifiers. In examples disclosed herein, only one of the multi-stage power amplifiers is activated at a given time. In this regard, the bias circuit can generate the bias signals to collectively activate one of the multi-stage power amplifiers, while deactivating the rest of the multi-stage power amplifiers. As such, it may be possible to control a larger number of power amplifier stages based on a smaller number of bias signals. As a result, it may be possible to eliminate a biasing bump pad(s) from the power amplifier apparatus, thus helping to reduce the footprint and cost of the power amplifier apparatus.

The method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The method includes intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The system includes a power amplification device capable of minimizing the effect of envelope impedance. The power amplification device may be incorporated in a terminal and a base station.

The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long term evolution (LTE). The present disclosure is to amplify transmission signals in a wireless communication system, and a transmitting device may include an antenna array including a plurality of antenna elements, a plurality of amplification chains for amplifying signals transmitted through the plurality of the antenna elements, and a power supply line for supplying powers to the plurality of the amplification chains. Herein, the powers used by power amplifiers included in at least one amplification chain of the plurality of the amplification chains may be divided by filtering or by independent pads and branch-lines.

A signal amplifier device is provided to ensure the continuity of the gain of an amplifier. The signal amplifier device includes a main path and a sub path connected in parallel to the main path. A main path first amplifier circuit amplifies an input signal on the main path. A main path second amplifier circuit includes a common-gate transistor connected in series with an output of the main path first amplifier circuit without sharing a DC current. On the main sub path, the sub path amplifier circuit amplifies the input signal by using a gain lower than the maximum gain in the main path.

A current reuse type FET amplifier according to the present invention has a capacitance provided between a drain of a first FET in a first stage and a gate of a second FET in a next stage, electrically separates a gate voltage of the second FET from a drain voltage of the first FET, and includes a control circuit controlling the gate voltage of the first FET and the gate voltage of the second FET so that a variation of a drain current of the second FET and a variation of a drain voltage of the first FET are reduced in accordance with a variation of a saturation current Idss of the FET. Furthermore, the current reuse type FET amplifier according to the present invention uses only a depression mode FET to provide a circuit configuration operable with a positive single power source.

An multistage amplifier includes first to third FETs, a drain of the second FET is connected to a gate of the third FET in an AC manner, a source thereof is grounded in a DC manner, a drain of the first FET is connected to a gate of the second FET in an AC manner, a source thereof is grounded in a DC manner, a gate thereof receives a high frequency signal, a drain of the third FET receives a bias current and outputs an amplified signal, a source thereof is grounded in an AC manner, the drains of the first and second FETs are connected to the source of the third FET in a DC manner via a transmission line having an electrical length of /4 when a wavelength of the high frequency signal is , and a size of third FET is greater than other FETs.

A positive-side power supply terminal (1-1a) of a differential amplifier (1-1) is connected to a positive-side power supply line (L1). A negative-side power supply terminal (1-2b) of a differential amplifier (1-2) is connected to a negative-side power supply line (L2). A negative-side power supply terminal (1-1b) of the differential amplifier (1-1) and a positive-side power supply terminal (1-2a) of the differential amplifier (1-2) are connected to each other. A final-stage amplifier (2) is connected between the positive-side power supply line (L1) and the negative-side power supply line (L2).