Methods and devices for a cascode differential input pair with low headroom voltage and high output impedance are presented. The cascode differential input pair includes first and second input (cascode) stages, each including a common-source regular transistor in series connection with a common-gate intrinsic transistor. Sources of the regular transistors are tied, and gates of the intrinsic transistors are tied. A gate voltage to the intrinsic transistors is provided by a source voltage at the sources of the regular transistors, the source voltage based on a common mode input voltage of the cascode differential input pair. According to one aspect, the cascode differential input pair is part of a differential amplifier that includes a current source coupled to the sources of the regular transistors, and a load coupled to drains of the intrinsic transistors.

An amplification device includes a signal input terminal, a signal output terminal, an amplification unit, a coupler, an inductive element and a capacitive element. The amplification unit includes an input terminal and an output terminal, where the input terminal is coupled to the signal input terminal. The coupler includes an input terminal, an output terminal and a coupling terminal, where the input terminal is coupled to the output terminal of the amplification unit, and the output terminal is coupled to the signal output terminal. The inductive element is coupled to the coupler in parallel and includes a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the amplification unit, and the second terminal is coupled to the output terminal of the coupler. The capacitive element is coupled between the output terminal of the coupler and a reference voltage terminal.

An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. A power amplifier may include multiple amplifier stages. Current sharing or reuse may occur between two amplifier stages in the power amplifier via a current flow path between the two amplifier stages. A power supply voltage line may be connected to the current flow path and may provide the downstream amplifier stage with a supplemental supply current based on which the downstream amplifier stage can amplify a radio-frequency signal received from the upstream amplifier stage.

A receiver circuit for double data rate memory is shown, which is operative to receive an input signal. The receiver circuit has two separated input circuits and a load-stage circuit. The first input circuit and the second input circuit in the input stage handle signals of non-overlapping signal swings. The input signal is received by an enabled input circuit of the first and the second input circuits. The load-stage circuit is coupled to the enabled input circuit to form a hybrid cascode circuit of a common-source and common-gate design.